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Counting
8.2.5
Interrupt Generation and Processing
Status bits REF1, REF2, UEBL and UEBS can trigger an interrupt and are stored in the interrupt
request bytes on the IP with their positive-going edges as RF1, RF2, UEB and UBS ( Section 8.3.3).
Reading the interrupt request bytes
After an interrupt request, an interrupt service organization block is called by the CPU. You must
call a control FB in this interrupt OB and parameterize "Read interrupt request bytes" with
FCT=3. The control FB transfers the interrupt request bytes of both channels to the specified DB
(DW 20 and 21). By evaluating these bytes in the interrupt service OB, you can react in a way
appropriate to the cause of the interrupt.
Reading these bytes has the following effect:
•
the bits in the interrupt request bytes on the IP are reset
•
the interrupt request is withdrawn by the IP
•
status bit UEBL is reset if this was the error which caused the interrupt.
As the interrupt request bytes are read across all channels, the current status can only be read
once from the IP and only the DB parameterized in the control FB can be directly updated.
Masking the interrupts
You can mask all bits with interrupt capability in the relevant channel by setting control bit AMSK
(D 17.15). Masked interrupts do not result in an interrupt request and are not stored in the
interrupt request bytes, i.e. they are lost.
Calling the interrupt service OBs in the S5-150U and S5-155U (150 mode)
In the S5-150U and S5-155U (150 mode), the relevant interrupt service OB is called at the next
block boundary on a signal change in a bit in PY 0. Using the parameter ABIT in configuring
FB 171 ( Section 8.3.1) you can specify whether the interrupt service OB is to be called on every
change or only on a change from 0 to 1.
Setting the ABIT parameter:
ABIT
: KY x,y
•
x>0
: the interrupt OB is called on every signal transition.
•
x=0, y=0 to 7
: the interrupt OB is called only on a signal transition from 0 to 1.
Note
Please observe the description of the encoder signals and the timing requirements
for counting mode presented in Chapter 13.
Detailed information on response times is presented in Chapter 12.
8-6
y must be set to the number of the bit in I/O byte 0 which you set on
switchbank S1 ( Section 5.1.2).
IP 240
EWA 4NEB 811 6120-02a
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