Status And Job Request Register (Offset 15); Contents Of The Status Register; The Idle Bit; The Err Bit - Siemens Simatic S5 IP 240 Manual

Direct Data Interchange with the IP 240
In the following, it has been assumed that the channel has been configured with standard FB 167
for positioning mode, with FB 169 for position decoding mode, or with FB 171 for counting mode.
11.1

Status and Job Request Register (Offset 15)

The IP 240's status register can be read out and its job request register written to under this
absolute address (module start address+15).
11.1.1 Status Register
The status register provides information about the status of job order processing on the IP 240 as
well as information on channel configuration.

Contents of the status register:

Bit 7 Bit 6
IP252 IDLE2
Each time you address the transfer buffer (offset 0 to 14), you must first read the status register.
Evaluate the bits in this register as follows:

1) The IDLE bit:

The IP 240 sets this bit to "0" when the channel was correctly configured.
If this bit is set, you must first call the relevant configuring FB.

2) The ERR bit:

The IP 240 sets this bit to "1" when an error has been flagged on the IP 240.
You must read and analyze the error code. The last attempted data interchange must be
retried with correct values.
Once the error code has been read, the ERR bit is reset on the IP 240.
3) The AFRT bit:
The IP 240 sets this bit to "1" when the last communication cycle was completed without error
( this bit is "1" following configuring with the standard FBs).
If a data interchange is aborted and the DFRT bit is set, communication with the IP 240 must
be reset prior to the start of a new Write or Read cycle. To do so, you must enter 40
job request register.
4) The DFRT bit:
The IP 240 sets this bit to "1",
• when the required data were made available in the transfer buffer during a Read cycle
and can be read out by the S5 CPU or
• when the data entered in the transfer buffer by the S5 CPU during a Write cycle was
fetched.
11-2
Bit 5 Bit 4
IDLE1 ERR
Bit 3 Bit 2
- DFRT
IP 240
Bit 1 Bit 0
AERK AFRT
in the IP's
H
EWA 4NEB 811 6120-02a