Flexible Swj-Dp Pin Assignment; Table 2. Debug Port Pin Assignment; Table 3. Swj I/O Pin Availability - ST STM32F10 Series Application Note

Debug management
Table 2.
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
JNTRST
4.3.2

Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as
dedicated pins immediately usable by the debugger host (note that the trace outputs are not
assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements a register to disable some part or all of the
SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This
register is mapped on an APB bridge connected to the Cortex™-M3 system bus. This
register is programmed by the user software program and not by the debugger host.
Table 3.
Full SWJ (JTAG-DP + SW-DP) - reset state
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
Table 3 shows the different possibilities to release some pins.
For more details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference
manuals, available from the STMicroelectronics website www.st.com.
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Debug port pin assignment
JTAG debug port
Type Description
JTAG test mode
I
selection
I JTAG test clock
I JTAG test data input
O JTAG test data output
I JTAG test nReset
SWJ I/O pin availability
Available Debug ports
Doc ID 13675 Rev 7
SW debug port
Type Debug assignment
Serial wire data
I/O
input/output
I Serial wire clock
- -
TRACESWO if async trace
-
is enabled
- -
SWJ I/O pin assigned
PA13 / PA14 /
PA15 /
JTMS/ JTCK/
JTDI
SWDIO SWCLK
X X
X X
X X
Released
AN2586
Pin
assignment
PA13
PA14
PA15
PB3
PB4
PB3 / PB4/
JTDO JNTRST
X X X
X X