Reset And Power Supply Supervisor; Power On Reset (Por) / Power Down Reset (Pdr); Figure 3. Power On Reset/Power Down Reset Waveform - ST STM32F10 Series Application Note

Power supplies
Figure 2.
1. Optional. If a separate, external reference voltage is connected on V
1 µF) must be connected.
2. V + is either connected to V
REF
3. N is the number of V
1.3

Reset and power supply supervisor

1.3.1

Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from
2 V.
The device remains in the Reset mode as long as V
V
POR/PDR
power on/power down reset threshold, refer to the electrical characteristics in the low-
density, medium-density, high-density, XL-density, and connectivity line STM32F10xxx
datasheets.
Figure 3.
8/28
Power supply scheme
V
BAT
V
Battery
V
DD
N × 100 nF
+ 1 × 10 µF
DDA
and V inputs.
DD SS
, without the need for an external reset circuit. For more details concerning the
Power on reset/power down reset waveform
V
DD
RESET
Doc ID 13675 Rev 7
STM32F10xxx
V
BAT
REF+
V
DDA
V
SSA
V
DD 1/2/3/.../N
V
REF–
V
SS 1/2/3/.../N
or to V .
REF
DD
POR
40 mV
hysteresis
Temporization
t
RSTTEMPO
V
REF
100 nF + 1 µF
V
DD
(note 1)
100 nF + 1 µF
ai14865b
, the two capacitors (100 nF and
REF+
is below a specified threshold,
PDR
ai14364
AN2586