Interrupts - Toshiba TMP91C824F Data Book

3.4 Interrupts

Interrupts are controlled by the CPU Interrupt Mask Register SR<IFF2:0> and by the
built-in interrupt controller.
The TMP91C824 has a total of 37 interrupts divided into the following five types:
•
Interrupts generated by CPU: 9 sources
(Software interrupts,Illegal Instruction interrupt)
•
Internal interrupts: 23 sources
•
Interrupts on external pins (NMI and INT0 to INT3): 5 sources
A (fixed) individual interrupt vector number is assigned to each interrupt.
One of seven (variable) priority level can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts are fixed at 7 as the highest level.
When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU.If
multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest
priority to the CPU.(The highest priority is level 7 using for non-maskable interrupts.)
The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register
<IFF[2:0]>. If the priority level of the interrupt is higher than the value of the interrupt mask register, the CPU
accepts the interrupt.
The interrupt mask register <IFF[2:0]> value can be updated using the value of the EI instruction ("EI num"
sets <IFF[2:0]> data to num).
For example, specifying "EI 3" enables the maskable interrupts which priority level set in the interrupt
controller is 3 or higher, and also non-maskable interrupts.
Operationally, the DI instruction (<IFF[2:0]> ="7") is identical to the "EI 7" instruction. DI instruction is
used to disable maskable interrupts because of the priority level of maskable interrupts is 0 to 6. The EI
instruction is vaild immediately after execution.
In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a micro DMA
interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes) automatically in micro DMA
mode, therefore this mode is used for speed-up interrupt processing, such as transferring data to the internal or
external peripheral I/O. Moreover,TMP91C824 has software start function for micro DMA processing request
by the software not by the hardware interrupt.
Figure 3.4.1 shows the overall interrupt processing flow.
91C824-36
TMP91C824