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Port
Pin name
Port 8
P80 to P87
P83
Port B
PB0 to PB6
PB0
PB1
PB2
PB3
PB4
PB5
PB6
Port C
PC0 to PC5
PC0
PC1
PC2
PC3
PC4
PC5
Port D
PD5 to PD7
PD5
PD6
PD7
Port Z
PZ2 to PZ3
PZ2
PZ3
(note1): PORT1 is only use for PORT or DATA bus(D8 to D15) by setting AM1 and AM0 pins.
(note2): As for input ports of SIO1 and SIO2: (OPTRX0,OPTTX0,TXD0,TRX0,SCCLK0,/CTS0, TXD1,TRX1,SCCLK1,/CTS1),
logical selection for output data or input data is determined by the output latch register Pn of each port.
(note3): In case using P71 and P72 for SDA and SCL as open-drain ports, set to P7ODE<ODEP71:ODEP72>.
(note4): In case using P80 to P87 for analog input ports of A/D converter, set to ADMOD1<ADCH2:ADCH1:ADCH0>.
(note5): In case using P83 for ADTRG input port, set to ADMOD1<ADTRGE>.
(note6): In case using PC1 for RXD0 port, set "1" to P7FC2<P70FC>.
Table 3.5.3 I/O Registers and Specifications (2/2)
Specification
Input port
AN0 to 7 input
(note4)
＿＿＿＿＿＿
ADTRG input
(note5)
Input port
Output port
TA0IN input
TA1OUT output
TA3OUT output
INT0 input
INT1 input
INT2 input
INT3 input
Input port
Output port
TXD0 output
(Note2)
RXD0 input
(Note2) (Note6)
SCLK0 input
(Note2)
SCLK0 output
(Note2)
＿＿＿＿＿
CTS0 input
(Note2)
TXD1 output
(Note2)
RXD1 input
(Note2)
SCLK1 input
(Note2)
SCLK1 output
(Note2)
＿＿＿＿＿
CTS1 input
(Note2)
Output port
SCOUT output
/ALARM output
/MLDALM output
MLDALM output
Input port (Without PU)
Input port (with PU)
Output port
＿＿＿＿
HWR output
＿＿
R/
W output
91C824-53
X: Don't care
I/O register
Pn
PnCR
PnFC
X
None
X
X
X
0
0
X
1
0
X
0
None
X
1
1
X
1
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
0
X
1
0
1
1
1
1
0
None
1
0
0
1
1
1
1
0
0
1
1
1
1
0
None
1
0
0
1
1
1
1
0
0
X
0
X
1
None
1
1
0
1
X
1
0
0
0
1
0
0
X
1
0
X
1
1
X
1
1
TMP91C824
PnFC2
None
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