Toshiba TMP91C824F Data Book page 124

3.9.1 Block diagrams
Figure 3.9.2 is a block diagram representing Serial Channel 0.
φT0
2 4
φT2
Serial clock generation circuit
BR0CR
<BR0CK1, 0>
φ
T0
φ
T2
φ
T8
φ
T32
f
SYS
SCLK0
concurrent
with PC2
I/O Interface Mode
SCLK0
concurrent
with PC2
(UART only ÷ 16)
RXDCLK
SC0MOD0
<RXE>
Receive Buffer1 (shift register)
RXD0
concurrent
with PC1
RB8 Receive Buffer2 (SC0BUF)
prescaler
8 16 32 64
φT8 φT32
BR0CR BR0ADD
<BR0S3 to 0> <BR0K3 to 0>
BR0CR
<BR0ADDE>
Baud rate
generator
÷2
Receive SC0MOD0 Serial channel
Counter interrupt
<WU>
control
Receive
Control
SC0CR
<PE>
Parity control
Error flag
SC0CR
<OERR><PERR><FERR>
Internal bus
Figure 3.9.2 Block diagram of the Serial Channel 0 (SIO0)
91C824-121
TA0TRG
(from TMRA0)
UART
Mode
SC0MOD0 SC0MOD0
<SC1, SC0> <SM1, SM0>
I/O
interface mode
SC0CR
<IOC>
Transmision
(UART only ÷ 16)
TXDCLK
Transmission
<EVEN>
Transmission Buffer (SC0BUF)
TB8
TMP91C824
SIOCLK
INT request
INTRX0
INTTX0
counter
Control
SC0MOD0
<CTSE>
CTS0
concurrent
with PC2
TXD0
concurrent
with PC0