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(2) External interrupt control
Symbol
NAME
Address
8CH
Interrupt
Input
IIMC
Mode
(no RMW)
control
INT0 level Enable
0
Rising edge detect INT
1
"H" level INT
NMI rising edge Enable
0
INT request generation at falling edge
1
INT request generation at rising/falling edge
(3) Interrupt request flag clear register
The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given
in Table 3.4 1, to the register INTCLR.
For example, to clear the interrupt flag INT0, perform the following register operation after
execution of the DI instruction.
INTCLR ← 0AH :
Symbol
NAME
Address
Interrupt
88H
INTCLR
Clear
Control
(no RMW)
(4) Micro DMA start vector registers
This register assigns micro DMA processing to which interrupt source. The interrupt source with
a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA
start source.
When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt
corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register
is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro
DMA processing, set the micro DMA start vector register again during the processing of the micro
DMA transfer end interrupt.
If the same vector is set in the micro DMA start vector registers of more than one channel, the
channel with the lowest number has a higher priority.
Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the
interrupt generated in the channel with the lower number is executed until micro DMA transfer is
complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is
started for the channel with the higher number. (Micro DMA chaining)
7
6
-
I3EDGE
0
0
INT3EDGE
Always
Always
0: Rising
write"0"
write"0"
1: Falling
Clears interrupt request flag INT0.
7
6
CLRV5
91C824-48
5
4
3
I2EDGE
I1EDGE
W
0
0
0
INT2EDGE
INT1EDGE
0: Rising
0: Rising
1: Falling
1: Falling
5
4
3
CLRV4
CLRV3
W
0
0
0
Interrupt Vector
TMP91C824
2
1
I0EDGE
I0LE
NMIREE
0
0
INT0EDGE
INT0 mode
1: Operates
0: Rising
0: Edge
even on
1: Falling
1: Level
rising /
falling edge
of NMI
2
1
CLRV2
CLRV1
CLRV0
0
0
0
0
0
0
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