Toshiba TMP91C824F Data Book page 25

3.3.4 Prescaler clock controller
For the internal I/O (TMRA01 to 23, SIO0 to 1) there is a prescaler which can divide the clock.
The φT0 clock input to the prescaler is either the clock f
4. The setting of the SYSCR0 <PRCK0 to PRCK1> register determines which clock signal is input.
3.3.5 Clock doubler (DFM)
DFM outputs the f
oscillator, even though the internal clock is high-frequency.
A Reset initializes DFM to Stop status, setting to DFMCR0-register is needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time.
The following example shows how DFM is used.
DFMCR0 EQU
DFMCR1 EQU
LD
LD
LUP: BIT
JR
LD
X: Don't care
ACT1:0
DFM output: f
DFM
Lockup timer
<DLUPFG>
System clock f
SYS
(note) Input frequency limitation and correction for DFM
Recommend to use Input frequency(High speed oscillation) for DFM in the following condition.
f = 4 ~ 6.75MHz (Vcc = 2.7~ 3.6V) : write 0BH to DFMCR1
OSCH
f = 2 ~ 2.5MHz (Vcc = 2.0V ±10%) : write 1BH to DFMCR1
OSCH
clock signal, which is four times as fast as f
DFM
00E8H
00E9H
(DFMCR1),00001011B
(DFMCR0), 01X0XXXXB
5, (DFMCR0)
NZ, LUP
(DFMCR0), 10X0XXXXB
01
Counts up by f
OSCH
During lock-up
Starts DFM operation.
Starts lock-up.
91C824-22
divided by 4 or the clock fc/16 divided by
FPH
OSCH
DFM parameter setting
12
; Set lock-up time to 2 /4 MHz
Enables DFM operation and starts lock-up
;
Detects end of lock-up
;
; Changes fc from 4 MHz to 16 MHz.
After lock-up
Changes from 4 MHz to 16 MHz.
Ends of lock-up
TMP91C824
. It can use the low-frequency
.
10