Toshiba TMP91C824F Data Book page 225

4.5 Serial Channel Timing (I/O Internal Mode)
(1) SCLK Input Mode
Symbol Parameter
T SCLK Period
SCY
Output Data
→ SCLK
T
OSS
Rising/Falling
Edge*
SCLK Rising/Falling Edge*
T
OHS
→ Output Data Hold
SCLK Rising/Falling Edge*
T
HSR
SCLK Rising/Falling Edge*
T
SRD
→ Valid Data Input
Valid Data Input →
T
RDS
SCLK Rising/Falling Edge*
(2) SCLK Output Mode
Symbol Parameter
T SCLK Period
SCY
Output Data → SCLK Rising
T
OSS
SCLK Rising/Falling Edge*
T
OHS
→ Output Data Hold
SCLK Rising/Falling Edge*
T
HSR
→ Input Data Hold
SCLK Rising/Falling Edge*
T
SRD
→ Valid Data Input
Valid Data Input →
T
RDS
SCLK Rising/Falling Edge*
(note): SCLK Rinsing/Falling Edge : The rising edge is used in SCLK Rising Mode.
27MHz and 10MHz values are calculated from t
SCLK
Output Mode/
Input Mode
SCLK
(Input Mode)
OUTPUT DATA
TxD
INPUT DATA
RxD
Min
16X
/2 − 4X − 110
Vcc=3V±10％ t
SCY
/2 − 4X − 180
Vcc=2V±10％ t
SCY
t /2 + 2X + 0
SCY
3X + 10
→ Input Data Hold
Min
16X
/2 − 40
t
SCY
/Falling Edge*
/2 − 40
t
SCY
0
1X + 180
The falling edge is used in SCLK Falling Mode.
t
t
OSS
Valid
91C824-222
Variable
Max Min
1.6
290
220
1000
310
− 0
t
SCY
0 0
Variable
Max Min
8192X 1.6
760
760
0
− 1X − 180
t
SCY
280
=16X case.
SCY
SCY
t
OHS
0 1
t
RDS
t
SRD
0 1
Valid
TMP91C824
10 MHz 27 MHz
Max Min Max
0.59
38
---
370
121
1600 592
0
10 MHz 27 MHz
Max Min Max
819 0.59 303
256
256
0
1320 375
217
2
t
HSR
2
Valid Valid
Unit
µ s
ns
ns
ns
ns
ns
ns
Unit
µ s
ns
ns
ns
ns
ns
3
3