Toshiba TMP91C824F Data Book page 24

(2) Clock gear controller
When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = 0, f
according to the contents of the Clock Gear Select Register SYSCR1<GEAR0 to GEAR2> to either
fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
consumption.
Example 3
Changing to a high-frequency gear
SYSCR1 EQU
LD
LD
X: Don't care
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2-0> register.It is necessary the
warmming up time until changing after writing the register value.
There is the possibility that the instruction next to the clock gear changing instruction is executed by the
clock gear before changing.To execute the instruction next to the clock gear switching instruction by the clock
gear after changing,input the dummy instruction as follows (instruction to execute the write cycle).
(Example)
SYSCR1 EQU
LD
LD
Instruction to be executed after clock gear has changed
(3) Internal clock terminal out function
It can out internal clock(f
PD5 pin function is set to SCOUT output by the following bit setting.
: PDFC<PD5F>='1'
Output clock select
:Refer to SYSCR2<SCOSEL> bit setting
HALT mode
SCOUT select
<SCOSEL>='0'
<SCOSEL>='1'
00E1H
(SYSCR1), XXXX0000B ;
(SYSCR1), XXXX0100B ;
00E1H
(SYSCR1), XXXX0001B ;
(DUMMY), 00H ;
or f ) from PD5/SCOUT.
SYS S
NORMAL
SLOW
IDLE2
f clock out
S
f clock out
SYS
91C824-21
Changes f to fc/2.
SYS
Changes f to fc/32.
SYS
Changes f to fc/4.
SYS
Dummy instruction
HALT mode
IDEL1
'0' or '1' fix out
TMP91C824
is set
FPH
reduces power
FPH
STOP