Toshiba TMP91C824F Data Book page 6

ADTRG(P83)
AN0 to AN7
(P80 to P87)
AVCC, AVSS
VREFH, VREFL
TXD0 (PC0)
RXD0 (PC1)
SCLK0/CTS0 (PC2)
TXD1 (PC3)
RXD1 (PC4)
SCLK1/ CTS1(PC5)
OPTRX0,SCK (P70)
(P71)
OPTTX0,SO/SDA
(P72)
SI/SCL
TA0IN (PB0)
TA1OUT (PB1)
TA3OUT (PB2)
CPU (TLCS-900/L1)
10-BIT 8CH
XW A
XBC
A/D
XDE
CONVERTER
XHL
XIX
XIY
SIO/UART/IrDA
XIZ
(SIO0) XSP
SIO/UART
(SIO1)
SERIAL BUS
W DT
I/F(SBI)
(W atch
8BIT TIMER DogTimer)
(TMRA0)
8BIT TIMER
(TMRA1)
8BIT TIMER
(TMRA2)
8BIT TIMER
(TMRA3)
PORT 6
8KB RAM
PORT 8
PORT B
PORT C
PORT D
Figure 1.1 TMP91C824F Block Diagram
91C824-3
H-OSC
W A
Clock Gear,
B C
Clock Doubler
D E
H L
L-OSC
IX
IY
IZ
SP
32 bit
SR F
PC
PORT 1
PORT 2
PORT 5
CS/W AIT
CONTROLLER
(4-BLOCK)
MMU
INTERRUPT
CONTROLLER
MELODY/
ALARM-OUT
RTC
( ) : Initial Function After Reset
TMP91C824
DVCC [3]
DVSS [3]
X1
X2
EMU0
EMU1
XT1
XT2
SCOUT(PD5)
RESET
AM0
AM1
D0 to D7
A0 to A7
A8 to A15
P10 to P17(D8 to D15)
P20 to P27
(A16 toA23)
RD
W R
HW R(P52)
W AIT (P53)
BUSRQ (P54)
BUSAK(P55)
R/W (P56)
CS0 toCS3
,CS2A ∼ CS2E
(P60 to P67)
NMI
INT0 to INT3
(PB3 to PB6),
MLDALM(PD7)
ALARM,MLDALM(PD6)