Toshiba TMP91C824F Data Book page 254

(2) Points to note
a) AM0 and AM1 pins
This pin is connected to the VCC or the VSS pin. Do not alter the level when the pin is active.
b) EMU0 and EMU1
Open pins.
c) Reserved address areas
The TMP91C815 does not have any reserved areas.
d) Warm-up counter
The warm-up counter operates when STOP Mode is released, even if the system is using an external
oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request
and output of the system clock.
e) Programmable pull-up resistance
The programmable pull-up resistor can be turned ON/OFF by a program when the ports are set for use
as input ports. When the ports are set for use as output ports, they cannot be turned ON/OFF by a program.
The data registers (e.g. Px) are used to turn the pull-up/-down resistors ON/OFF. Consequently
read-Modify-write instructions are prohibited.
f) Bus release function
It is described note point in "3.5 Port Function" that pin's condition at bus release condition.
Please refer that.
g) Watchdog timer
The watchdog timer starts operation immediately after a Reset is released. When the watchdog timer is
not to be used, disable it.
h) AD converter
The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power
consumption. When STOP Mode is used, disable the resistor using the program before the HALT
instruction is executed.
i) CPU (micro DMA)
Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers in the CPU (e.g.
the Transfer Source Address Register (DMASn)).
j) Undefined SFR
The value of an undefined bit in an SFR is undefined when read.
k) POP SR instruction
Please execute the POP SR instruction during DI condition.
l) Releasing the HALT mode by requesting an interruption
Usually, interrupts
(/NMI,INT0-3,INTKEY,INTRTC,INTALM0 to 4) which can release the HALT mode may
not be able to do so if they are input during the period CPU is shifting to the HALT mode(for
about 5 clocks of f
interrupt request is kept on hold internally)
If another interrupt is generated after it has shifted to HALT mode completely, release halt
status can be released without difficulty.The priority of this interrupt is compared with that
of the interrupt kept on hold internally,and the interrupt with higher priority is handled
first followed by the other interrupt..
can release
) with IDLE1 or STOP mode(IDLE2 is not applicable).(In this case,an
FPH
91C824-
all halts status. However,
251
TMP91C824
the interrupts