Toshiba TMP91C824F Data Book page 190

(5) A/D conversion time
84 states (10.5 µs @ f
(6) Storing and reading the results of A/D conversion
The A/D Conversion Data Upper and Lower Registers (ADREG04H/L to ADREG37H/L) store
the A/D conversion results. (ADREG04H/L to ADRG37H/L are read-only registers.)
In Channel Fixed Repeat Conversion Mode, the conversion results are stored successively in
registers ADREG04H/L to ADRG37H/L. In other modes, the AN0 and AN4, AN1 and AN5, AN2
and AN6, and AN3 and AN7 conversion results are stored in ADREG04H/L, ADREG15H/L,
ADREG26H/L and ADREG37H/L respectively.
Table 3.11.3 shows the correspondence between the analog input channels and the registers which
are used to hold the results of A/D conversion.
Table 3.11.3 Correspondence Between Analog Input Channels and
A/D Conversion Result Registers
Analog input channel
(Port A)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
<ADRxRF>, bit "0" of the A/D conversion data lower register, is used as the A/D conversion
data storage flag. The storage flag indicates whether the A/D conversion result register has been
read or not. When a conversion result is stored in the A/D conversion result register, the flag is set to
"1". When either of the A/D conversion result registers (ADREGxH or ADREGxL) is read, the flag
is cleared to "0".
Reading the A/D conversion result also clears the A/D Conversion End flag ADMOD0<EOCF> to
"0".
= 16MHz) are required for the A/D conversion for one channel.
FPH
A/D Conversion Result Register
Conversion modes other
than at right
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
91C824-187
Channel fixed repeat
conversion mode
(every 4th conversion)
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
TMP91C824