Toshiba TMP91C824F Data Book page 74

(2) Port C1, C4 (RXD0, 1)
Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case
of use RXD0/RXD1, it is possible to logical invert by setting the register PC<PC1,PC4>.
And input data of SIO0 can be select from RXD/PC1 pin or OPTRX0/P70 by setting the register
PCFC2<P70F2>.
Reset
Ditection control
(On bit basis)
PCCR write
S
Output latch
PC write
PC read
RXD0PC1,
RXD1
(3) Port C2(/CTS0,SCLK0),C5( /CST1,SCLK1)
Port C2 and C4 are I/O port pins and can also is used as /CTS input or SCLK input/output for the
serial channels. In case of use /CTS,SCLK, it is possible to logical invert by setting the register
PC<PC2,PC5>.
Reset
Ditection control
(On bit basis)
PCCR write
Function control
(On bit basis)
PCFC write
S
Output latch
PC write
Logical
invert
SCLK0, 1
output
PC read
/CTS0,1
SCLK0, 1
input
Logical invert
S B
Selector
A
Logical invert
Figure 3.5.20 Port C1 and C4
A S
Selector
B
S B
Selector
A
Figure 3.5.21 Port C2 and C5
91C824-71
TMP91C824
PC1 (RXD0)
PC4 (RXD1)
PC2 (SCLK0,/CTS0)
PC5 (SCLK1,/CTS1)