Toshiba TMP91C824F Data Book page 197

3.12.3 Operation
The watch dog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1,WDTP0> has elapsed. The watch dog timer must be cleared "0" by software before
an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if runaway occurs) due to causes
such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will
overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (runaway) due to
the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of
an anti-malfunction program.
The watch dog timer works immediately after reset.
The watch dog timer does not operate in IDLE1 or STOP mode,
as the binary counter continues counting during bus release (When BUSAK goes Low).
When the device is in IDLE2 Mode, the operation of WDT depends on the WDMOD<I2WDT> setting.
Ensure that WDMOD<I2WDT> is set before the device enters IDLE2 Mode.
Example: ! Clear the binary counter.
WDCR
" Set the watchdog timer detection time to 2
WDMOD ← 1 0 1 - - - X X
# Disable the watchdog timer.
WDMOD ← 0 - - - - - X X
WDCR
← 0 1 0 0 1 1 1 0
← 1 0 1 1 0 0 0 1
91C824-194
Write the clear code (4EH).
17
/ f .
SYS
Clear WDTE to "0".
Write disable code (B1H).
TMP91C824