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(6) The Receiving Buffers
To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure.
Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or
8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving
Buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads
Receiving Buffer 2 (SC0BUF). Even before the CPU reads receiving Buffer 2 (SC0BUF), the
received data can be stored in Receiving Buffer 1. However, unless Receiving Buffer 2 (SC0BUF)
is read before all bits of the next data are received by Receiving Buffer 1, an overrun error occurs. If
an Overrun error occurs, the contents of Receiving Buffer 1 will be lost, although the contents of
Receiving Buffer 2 and SC0CR<RB8> will be preserved.
SC0CR<RB8> is used to store either the parity bit – added in 8-Bit UART Mode – or the most
significant bit (MSB) – in 9-Bit UART Mode.
In 9-Bit UART Mode the wake-up function for the slave controller is enabled by setting
SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the value of
SC0CR<RB8> is 1.
(7) Transmission counter
The transmission counter is a 4-bit binary counter which is used in UART Mode and which, like
the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16
SIOCLK clock pulses.
SIOCLK
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16
1
2
TXDCLK
Figure 3.9.4 Generation of the transmission clock
(8) Transmission controller
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR<IOC> = 0, the data in the Transmission Buffer is
output one bit at a time to the TXD0 pin on the rising edge of the shift clock which is output on the
SCLK0 pin.
In SCLK Input Mode with the setting SC0CR<IOC> = 1, the data in the Transmission Buffer is
output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input, according
to the SC0CR<SCLKS> setting.
• In UART Mode
When transmission data sent from the CPU is written to the Transmission Buffer, transmission
starts on the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT.
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