Related Manuals for Altera Arria 10 GX
Summary of Contents for Altera Arria 10 GX
- Page 1 Arria 10 GX Transceiver Signal Integrity Development Kit User Guide 101 Innovation Drive UG-20005 Subscribe 2017.08.08 San Jose, CA 95134 Send Feedback www.altera.com...
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Page 2: Table Of Contents
FPGA Programming from Flash Memory..................5-16 FPGA Programming over External USB-Blaster...............5-19 Status Elements............................5-20 Setup Elements............................5-21 Clock Circuits............................. 5-22 Transceiver Dedicated Clocks...................... 5-22 General Purpose Clocks........................5-23 Embedded USB Blaster Clock...................... 5-24 General User Input/Output........................5-24 User-Defined Push Buttons......................5-25 Altera Corporation... - Page 3 Creating Flash Files Using the Nios II EDS..................... A-2 Programming Flash Memory Using the Board Update Portal..............A-3 Programming Flash Memory Using the Nios II EDS................A-3 Restoring the Flash Device to the Factory Settings.................A-4 Restoring the MAX V CPLD to the Factory Settings................A-4 Altera Corporation...
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Page 4: About This Development Kit
Spectra-Q engine enables new levels of design productivity for next generation programmable devices Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Page 5: Development Kit Package
Quartus Prime Pro Edition, Intel Quartus Prime Standard Edition, and Intel Quartus Prime Design Suite Lite Edition. • Intel Quartus Prime Pro Edition is optimized to support the advanced features in Altera's next generation FPGAs and SoCs, starting with the Arria 10 device family and requires a paid license. -
Page 6: Getting Started
5. In the Find/Activate Products dialog box, enter your development kit serial number and click Search. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. -
Page 7: Inspect The Board
7. Click Activate Selected Products and click Close. 8. When licensing is complete, Altera emails a license.dat file to you. Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus Prime software to enable the software. -
Page 8: Installing The Usb-Blaster Driver
FPGA programming. However, for the host computer and board to communicate, you must install the USB-Blaster driver on the host computer. Installation instructions for the USB-Blaster driver for your operating system are available on the Altera Altera Cable and Adapter Drivers Information website. -
Page 9: Development Board Setup
FACTORY_LOAD. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Page 10: Factory Default Switch Settings
The kit includes a MAX V CPLD design which contains the PFL megafunction. The design resides in the directory. <package dir>\examples\max5 1. When configuration is complete, LED D26 (CFGDN) illuminates signaling that the Intel Arria 10 GX FPGA device configured successfully. 2. If the configuration fails, the LED 24 (ERROR) illuminates. - Page 11 MSEL2 MSEL Setting SW13-4 VID_EN VID Enable SW13-5 FAN_ON Fan always ON OPEN SW13-6 MAX_BYPASS Bypass MAX V (Active OPEN Low) SW14-1 I2C_33V_SCL / LT_ I2C-Clock CLOSE SW14-2 I2C_33V_SDA / LT_ I2C-Data CLOSE Development Board Setup Altera Corporation Send Feedback...
- Page 12 UG-20005 Factory Default Switch Settings 2017.08.08 Figure 3-1: Factory Default Switch Settings CFP 2 FLASH FLASH MAX5 A10GX J 28 QSFP + J 29 SFP + Development Board Setup Altera Corporation Send Feedback...
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Page 13: Board Update Portal
• The Ethernet, power cables and development board that are included in the kit. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Page 14: Using The Board Update Portal To Update User Designs
Board Update Portal web page. 2. In the Hardware File Name field specify the .flash file that you either downloaded from the Altera website or created on your own. If there is a software component to the design, specify it in the same manner using the Software File Name field;... -
Page 15: Board Components
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. - Page 16 UG-20005 Board Overview 2017.08.08 Figure 5-1: Overview of the Arria 10 GX Transceiver Signal Integrity Development Board Features Table 5-1: Transceiver Signal Integrity Development Kit Components Board Reference Type Description Featured Devices FPGA Arria 10 GX1150 FPGA (10AX115F1932C) CPLD MAX V CPLD (5M2210ZF256), 256-pin...
- Page 17 Reference Clock / Program‐ 10 GX device and an LVDS trigger output at mable Oscillator board reference J104/J105. The external input is available at board reference J59 and J60. The default frequency is 625 MHz. Board Components Altera Corporation Send Feedback...
- Page 18 RJ-45 connector which provides a 10/100/ 1000 Ethernet connection through a Marvell 88E1111 PHY USB Type-B connector Connects a type-B USB cable Power Supply U209 LTM 2987 Linear Technology Power monitor device U225 LTC2974 Linear Technology Power monitor device Board Components Altera Corporation Send Feedback...
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Page 19: Arria 10 Fpga
• 3036 18-bit x 19-bit Multipliers • 32 Fractional Synthesis Phase-Locked Loops (PLLs) • 72 15Gbps Transceivers I/O Resources The table below summarizes the FPGA I/O usage by function on the Arria 10 GX transceiver signal integrity development board. Board Components Altera Corporation... - Page 20 UG-20005 I/O Resources 2017.08.08 Table 5-3: Arria 10 GX I/O Usage Summary Function I/O Count Description Configuration JTAG USB Blaster or JTAG Built-in USB-Blaster or JTAG 0.1-mm Header header for debugging MSEL [2:0] Configuration input pins to set configu‐ ration scheme...
- Page 21 Ethernet ENET_SGMII_TX_P/N Ethernet SGMII transmit data ENET_SGMII_RX_P/N Ethernet SGMII receive data ENET_RSTn Reset ENET_INTn Interrupt MDIO Ethernet Management Data IO Ethernet Management Data Clock Temperature Sense Temperature Sense Diodes Arria 10 internal sense diode Board Components Altera Corporation Send Feedback...
- Page 22 %) A10GX_CLK3Bp Global Clock input from SMA A10GX_CLK3Bn Global Clock input from SMA 100MHZ_LVDS_CLK3p Differential global clock 100MHZ_LVDS_CLK3n Differential global clock 100MHZ_LVDS_CLK2p Differential global clock 100MHZ_LVDS_CLK2n Differential global clock 100MHZ_LVDS_CLK1p Differential global clock Board Components Altera Corporation Send Feedback...
- Page 23 Differential REFCLK input to the left side of xcvr block 4D REFCLK_GXBR_4E_B Differential REFCLK input to the left side of xcvr block 4E REFCLK_GXBR_4H_B Differential REFCLK input to the left side of xcvr block 4H Board Components Altera Corporation Send Feedback...
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Page 24: Max V Cpld
The table below lists the MAX V CPLD Pin-out, the I/O signals present on the MAX V CPLD. Table 5-4: MAX V CPLD Device Pin-Out Schematic Signal Name MAX V CPLD Arria 10 GX Pin Number Description Pin Number FPGA_CONFIG_D0... - Page 25 UG-20005 5-11 MAX V CPLD 2017.08.08 Schematic Signal Name MAX V CPLD Arria 10 GX Pin Number Description Pin Number FPGA_CONFIG_D16 AW28 FPP Configuration Data Bus FPGA_CONFIG_D17 AV28 FPP Configuration Data Bus FPGA_CONFIG_D18 AY31 FPP Configuration Data Bus FPGA_CONFIG_D19 AY30...
- Page 26 UG-20005 5-12 MAX V CPLD 2017.08.08 Schematic Signal Name MAX V CPLD Arria 10 GX Pin Number Description Pin Number FM_A18 Flash address bus FM_A19 Flash address bus FM_A20 Flash address bus FM_A21 Flash address bus FM_A22 Flash address bus...
- Page 27 UG-20005 5-13 MAX V CPLD 2017.08.08 Schematic Signal Name MAX V CPLD Arria 10 GX Pin Number Description Pin Number FM_D24 Flash data bus FM_D25 Flash data bus FM_D26 Flash data bus FM_D27 Flash data bus FM_D28 Flash data bus...
- Page 28 UG-20005 5-14 MAX V CPLD 2017.08.08 Schematic Signal Name MAX V CPLD Arria 10 GX Pin Number Description Pin Number PGM_LED1 ---- Flash memory PGM select indicator 1 PGM_LED2 ---- Flash memory PGM select indicator 2 CLK_SEL ---- Clock Select (dipswitch set)
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Page 29: Configuration Elements
This section describes the FPGA, flash memory, and MAX V CPLD System Controller device program‐ ming methods supported by the Intel Arria 10 GX transceiver signal integrity development board. The Intel Arria 10 GX transceiver signal integrity development board supports three configuration methods: •... -
Page 30: Fpga Programming From Flash Memory
PC running Intel Quartus Prime software without requiring the external USB Blaster dongle. This design will convert USB data to interface with the Intel Arria 10 GX FPGA’s dedicated JTAG port. An LED (D4) is provided to indicate USB Blaster activity. The embedded USB blaster is automatically disabled when an external USB Blaster dongle is connected to the JTAG chain. - Page 31 UG-20005 5-17 FPGA Programming from Flash Memory 2017.08.08 Figure 5-4: MAX V + Flash FPP x32 Configuration Conceptual Diagram CCPGM Flash CTRL DATA[15:0] Arria 10 GX CONF_DONE MSEL[2:0] nSTATUS nCEO External host (MAX V or Microprocessor) DATA[31:0] PGMSEL nCONFIG DCLK The figure below shows a more detailed schematic block diagram for the MAX V + Flash FPP mode implementation.
- Page 32 DCLK and D[31:0] configuration pins at 50 MHz. The actual configuration data rate is limited by the flash read speed. Implementation will be done using an Altera MAX V 5M2210ZF256FBGA CPLD acting as the FPP download controller and two 1G Flash devices. The flash will be a Numonyx 1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF).
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Page 33: Fpga Programming Over External Usb-Blaster
FPGA Programming over External USB-Blaster 2017.08.08 the Intel Arria 10 GX FPGA. No arbitration is needed between the MAX V CPLD and Intel Arria 10 GX FPGA to access the Flash as the CPLD only has access prior to FPGA initialization. -
Page 34: Status Elements
Note: The Intel Arria 10 GX FPGA device is always available in the JTAG chain and cannot be bypassed. Pin 2 of the Intel Arria 10 GX FPGA and MAX V JTAG Header will be used to disable the embedded USB Blaster by connecting it to the embedded Blaster’s DEVOEn pin with a pull-up resistor. -
Page 35: Setup Elements
Program Select Push Button: After a POWER-ON or RESET (reconfiguration) event, the MAX V will configure the Intel Arria 10 GX FPGA in FPP mode with either the FACTORY POF or a USER defined POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. -
Page 36: Clock Circuits
Transceiver Dedicated Clocks The figure below shows the dedicated transceiver clocking that will be implemented for the FPGA. This clocking scheme will allow 4 different protocols to be running simultaneously by the Intel Arria 10 GX FPGA. Four differential clock sources are provided from an I2C programmable VCO oscillator to the dedicated REFCLK input pins of transceiver blocks on both sides of the FPGA. -
Page 37: General Purpose Clocks
4. Four 100 MHz clock outputs are provided from an SiLabs Si5338A-Custom clock buffer. • CLK0: 100MHz- LVDS standard • CLK1: 100MHz- LVDS standard • CLK2: 100MHz- 1.8V CMOS standard • CLK3: 100MHz- LVDS standard 5. One 125 MHz LVDS standard Oscillator output. Board Components Altera Corporation Send Feedback... -
Page 38: Embedded Usb Blaster Clock
A 24 MHz oscillator is dedicated for the embedded USB2 Blaster circuitry. The oscillator is used to clock the Cypress CY7C68013A USB2 PHY device. General User Input/Output This section describes the user I/O interface to the FPGA. This section describes the following elements: Board Components Altera Corporation Send Feedback... -
Page 39: User-Defined Push Buttons
The development board includes 8 user-defined push buttons and 4 system push buttons that allow you to interact with the Intel Arria 10 GX FPGA device. When you press and hold down the push button, the device pin is set to logic 0; when you release the push button, the device pin is set to logic 1. There is no board-specific function for these general user push buttons. -
Page 40: User-Defined Leds
LEDs that allow status and debugging signals to be driven to the LEDs from the designs loaded into the Intel Arria 10 GX FPGA device. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. -
Page 41: Transceiver Channels
I2C_5V_SDA I2C serial data Transceiver Channels The Intel Arria 10 GX transceiver signal integrity development board dedicates 29 transceiver channels from both the left and right sides of the device. Transceiver channels are allocated as shown in the table below... - Page 42 UG-20005 5-28 Transceiver Channels 2017.08.08 Figure 5-9: Arria 10 GX Transceiver Usage Block Diagram Block H Block H TX/RX (X4) TX/RX (X4) Backplane CFP2 Connector Block G Block G TX/RX (X4) TX/RX (X5) High-Density Block F Block F Connector TX/RX (X1) 2.4 mm Vertical...
- Page 43 GXB transmit GXBL_1E_RX0p AG42 GXB receive GXBL_1E_RX0n AG41 GXB receive GXBL_1E_RX1p AF40 GXB receive GXBL_1E_RX1n AF39 GXB receive GXBL_1E_RX3p AD40 GXB receive GXBL_1E_RX3n AD39 GXB receive GXBL_1E_RX4p AC42 GXB receive GXBL_1E_RX4n AC41 GXB receive Board Components Altera Corporation Send Feedback...
- Page 44 Note: TX4 p/n pins swapped at CFP2 connector J24B GXBL_1H_RX0p GXB receive Note: RX0 p/n pins swapped at CFP2 connector J24B GXBL_1H_RX0n GXB receive Note: RX0 p/n pins swapped at CFP2 connector J24B GXBL_1H_RX1p GXB receive GXBL_1H_RX1n GXB receive Board Components Altera Corporation Send Feedback...
- Page 45 GXB receive GXBR_4E_RX_4n GXB receive GXBR_4E_RX_5p GXB receive GXBR_4E_RX_5n GXB receive GXBR_4F_TX_0p GXB transmit GXBR_4F_TX_0n GXB transmit GXBR_4F_TX_1p GXB transmit GXBR_4F_TX_1n GXB transmit GXBR_4F_TX_2p GXB transmit GXBR_4F_TX_2n GXB transmit GXBR_4F_TX_3p GXB transmit GXBR_4F_TX_3n GXB transmit Board Components Altera Corporation Send Feedback...
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Page 46: Communication Ports
PHY device and the Altera Triple-Speed Ethernet Megacore MAC function. The device is an auto- negotiating Ethernet PHY with an SGMII interface to the FPGA. The Intel Arria 10 GX FPGA device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function must be provided in the FPGA for typical networking applications. -
Page 47: Flash Memory
Flash device. MAX V CPLD accesses will be for FPP configuration of the FPGA at power- on and board reset events. This will use the Altera PFL Megafunction. Arria 10 GX FPGA access to the FLASH’s user space will be done by Nios II for the BUP application. The flash will be wired for WORD mode operation to support FPPx32 download directly. - Page 48 B5 (U33/U34) FM_A14 Address Bus C5 (U33/U34) FM_A15 Address Bus D7 (U33/U34) FM_A16 Address Bus D8 (U33/U34) FM_A17 Address Bus A7 (U33/U34) FM_A18 Address Bus B7 (U33/U34) FM_A19 Address Bus C7 (U33/U34) FM_A20 Address Bus Board Components Altera Corporation Send Feedback...
- Page 49 E5 (U34) FM_D20 Data Bus G5 (U34) FM_D21 Data Bus G6 (U34) FM_D22 Data Bus H7 (U34) FM_D23 Data Bus E1 (U34) FM_D24 Data Bus E3 (U34) FM_D25 Data Bus F3 (U34) FM_D26 Data Bus Board Components Altera Corporation Send Feedback...
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Page 50: Power Supply
Some power rails on the board will have the option to be supplied from an external source via banana jack connectors by first removing a jumper for that power rail. Board Components Altera Corporation Send Feedback... - Page 51 Transceiver Reference Clock (Si53311) Buffers SS Clock Generator 3.3V Spread Spectrum/ Clock Select (ICS557) capability to core clock Programmable 1.8V/2.5V 1.8V/2.5V 100 MHz clock source to FPGA/ Clock Buffer MAX V core clock inputs Si5338A Board Components Altera Corporation Send Feedback...
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Page 52: Power Measurement
A10GX_1.8V power 1.8V FPGA I/O 12V Input Power 3.3V 3.3V 3.3V Input Power Power Distribution System The figure shows the power distribution system on the Intel Arria 10 GX transceiver signal integrity development board. Board Components Altera Corporation Send Feedback... -
Page 53: Temperature Sense
Temperature monitoring will be done by a MAX1619 dual temperature sense device. This device will allow temperature sensing of both the Intel Arria 10 GX FPGA die and board ambient. The MAX1619 is connected to the Intel Arria 10 GX FPGA by a 2-wire SMBus interface. Additionally, the OverTemp (OTn) and ALERTn signals from the MAX1619 is brought to the MAX V device to allow it to immediately sense a temperature fault condition and turn on the Intel Arria 10 GX FPGA's attached FAN. - Page 54 The fan will be controlled by the OverTemp signal from the MAX1619 and can be set to turn on when the Arria 10 GX FPGA die temperature exceeds a specified set point. Temperature fault set points can be programmed into the MAX1619. The HDL design code along with .sof/.pof files are provided to the user.
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Page 55: Board Test System
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Page 56: Preparing The Board
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applications before attempting to reconfigure the FPGA using the Intel Quartus Prime Programmer. With the power to the board OFF, following these steps: 1. Connect the USB cable to the board. Board Test System Altera Corporation Send Feedback... -
Page 57: Running The Board Test System
The Board Test System (BTS) will prompt you with a Version Selector window once opened. You can also open the Version Selector window through the Configure tab by clicking Select Silicon Version. Select the silicon version of the Intel Arria 10 GX FPGA device that is installed on your board. Board Test System... -
Page 58: Using The Board Test System
This section describes each control in the Board Test System application. The Configure Menu Use the Configure menu to select the design you want to use. Each design example tests different functionality that corresponds to one or more application tabs. Board Test System Altera Corporation Send Feedback... -
Page 59: The System Info Tab
The System Info tab shows information about the board’s current configuration. The tab displays the contents of the MAX V registers, the JTAG chain, the board’s MAC address, the flash memory map, and other details stored on the board. Board Test System Altera Corporation Send Feedback... - Page 60 • MAX V ver—Indicates the version of MAX V code currently running on the board. The MAX V code resides in the directory. Newer revisions of this <package dir>\examples\max5 Arria 10 GX Transceiver Signal Integrity Development Kit code might be available on the web page of the Altera website.
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Page 61: The Gpio Tab
0 to SRST or changing the PSO value can cause the Board Test System to stop running. JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain. The Intel Arria 10 GX FPGA device is always the first device in the chain. - Page 62 (SW2 and SW6). Change the switches on the board to see the graphical display change accordingly. User LEDs The User LEDs control displays the current state of the user LEDs. Toggle the LED buttons to turn the board LEDs on and off. Board Test System Altera Corporation Send Feedback...
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Page 63: The Flash Tab
Valid entries are 0x0000.0000 through 0x0FFF.FF80. Caution: If you enter an address outside of 0x0000.0000 to 0x07FF.FFFF flash memory address space, a warning message identifies the valid flash memory address range. Board Test System Altera Corporation Send Feedback... -
Page 64: The Xcvr #1 Tab
512K block. Flash Memory Map Displays the flash memory map for the Intel Arria 10 GX transceiver signal integrity development kit. The XCVR #1 Tab The XCVR #1 tab allows you to run transceivers QSFP, SFP+ and CFP2 loopback tests on your board. You can run the test using either electrical loopback modules or optical fibre modules. - Page 65 • Details - Shows the PLL lock and pattern sync status. Related Information • Status on page 6-14 Status • on page 6-16 Port Use the following controls to select an interface to apply PMA settings, data type and error control: Board Test System Altera Corporation Send Feedback...
- Page 66 5. DC Gain - Specifies the DC gain setting for the receiver equalizer in four stage mode. 6. VGA - Specifies the VGA gain value. Figure 6-8: PMA Settings Related Information • PMA Setting on page 6-15 PMA Setting • on page 6-17 Board Test System Altera Corporation Send Feedback...
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Page 67: The Xcvr #2 Tab
Run Control on page 6-15 Run Control • on page 6-17 The XCVR #2 Tab The XCVR #2 tab allows you to run a x4 backplane and x6 SMA (2.4 mm) loopback tests. Board Test System Altera Corporation Send Feedback... - Page 68 Refer to the Status section of the XCVR #1 Tab for related information. Related Information Status on page 6-11 Port Use the following controls to select an interface to apply PMA settings, data type and error control: • Amphenol • SMA Board Test System Altera Corporation Send Feedback...
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Page 69: The Xcvr #3 Tab
Refer to the Run Control section of the XCVR #1 Tab for related information. Related Information Run Control on page 6-13 The XCVR #3 Tab The XCVR #3 tab allows you to run x10 high density loopback test through BullsEye connector. Board Test System Altera Corporation Send Feedback... - Page 70 Refer to the Status section of the XCVR #1 Tab for related information. Related Information Status on page 6-11 Port Use the following control to select the high density interface to apply PMA settings, data type and error control: High Density (BullsEye) Board Test System Altera Corporation Send Feedback...
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Page 71: Power Monitoring
Power Monitor as a stand-alone application. The PowerMonitor.exe reside in the <package dir> \examples\board_test_system directory Note: You cannot run the stand-alone power application and the BTS application at the same time. Also, you cannot run power and clock interface at the same time. Board Test System Altera Corporation Send Feedback... -
Page 72: The Clock Control
<package dir>\examples\board_test_system The Clock Control communicates with the MAX V device on the board through the JTAG bus. The Si570 programmable oscillator is connected to the MAX V device through a 2-wire serial bus. Board Test System Altera Corporation Send Feedback... - Page 73 945 MHz and select frequencies to 1400 MHz. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target frequency control works in conjunction with the Set New Frequency control. Board Test System Altera Corporation Send Feedback...
- Page 74 The Set New Frequency control sets the Si570 programmable oscillator frequency to the value in the Target frequency control. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Note: Altera recommends resetting the FPGA logic after changing frequencies. Board Test System Altera Corporation...
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Page 75: Additional Information
Initial Release Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Page 76: Programming The Flash Memory Device
0x0001.0000 - 0001.FFFF Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. -
Page 77: Preparing Design Files For Flash Programming
User Design Reset 64 KB 0x0000.0000 - 0000.FFFF Attention: Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools. Preparing Design Files for Flash Programming You can obtain designs containing prepared .flash files from the... -
Page 78: Programming Flash Memory Using The Board Update Portal
7. Click Start to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100% 8. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II Command Shell. 9. In the Nios II command shell, navigate to the directory (or to <package dir>\factory_recovery... -
Page 79: Restoring The Flash Device To The Factory Settings
4. Set the correct board information and then click Restore. Please note the restore process takes about 10 minutes. Attention: To ensure that you have the most up-to-date factory restore files and information about Arria 10 GX Transceiver Signal Integrity Development Kit this product, refer to the page on the Altera website.