Board Component Blocks - Altera Cyclone III FPGA Reference Manual

General Description
1–2
Cyclone III FPGA Starter Board

Board Component Blocks

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Altera Cyclone III EP3C25F324 FPGA
25K logic elements (LEs)
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66 M9K memory blocks (0.6 Mbits)
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16 18x18 multiplier blocks
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Four PLLs
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214 I/Os
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Clock management system
One 50 MHz clock oscillator to support a variety of protocols
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The Cyclone III device distributes the following clocks from its
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on-board PLLs:
• DDR clock
• SSRAM clock
• Flash clock
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HSMC connector
Provides 12 V and 3.3 V interface for installed daughter cards
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Provides up to 84 I/O pins for communicating with HSMC
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daughter cards
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General user-interface
Four user LEDs
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Two board-specific LEDs
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Push-buttons:
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• System reset
• User reset
• Four general user push-buttons
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Memory subsystem
Synchronous SRAM device
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• 1-Mbyte standard synchronous SRAM
• 167-MHz
• Shares bus with parallel flash device
Parallel flash device
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• 16-Mbyte device for active parallel configuration and
storage
• Shares bus with SRAM device
DDR SDRAM device
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• 56-pin, 32-Mbyte DDR SDRAM
• 167-MHz
• Connected to FPGA via dedicated 16-bit bus
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Built-in USB-Blaster interface
Using the Altera EPM3128A CPLD
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For external configuration of Cyclone III device
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For system debugging using the SignalTap
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debugging console
Communications port for Board Diagnostic graphical user
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interface (GUI)
Reference Manual
® ®
and Nios
Altera Corporation
October 2007