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Altera MAX 10 User Manual

Altera MAX 10 User Manual

Fpga development kit
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MAX 10 FPGA Development Kit User
Guide
101 Innovation Drive
UG-01169
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2017.09.07
San Jose, CA 95134
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www.altera.com

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  • Page 1 MAX 10 FPGA Development Kit User Guide 101 Innovation Drive UG-01169 Subscribe 2017.09.07 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    Selecting the Internal Configuration Scheme................4-4 Switch and Jumper Settings......................4-5 Status Elements.............................4-7 Setup Elements............................. 4-8 General User Input/Output.........................4-8 Clock Circuitry.............................4-9 On-Board Oscillators........................4-10 Off-Board Clock Input/Output....................4-11 Components and Interfaces........................4-12 10/100/1000 Ethernet PHY......................4-12 Digital-to-Analog Converter......................4-15 HDMI Video Output........................4-16 Altera Corporation...
  • Page 3 USB to UART..........................4-23 Memory............................... 4-24 DDR3 Rev. B Board........................4-24 DDR3 Rev. C Board........................4-26 Flash..............................4-29 Power Distribution System........................4-31 Additional Information..................A-1 User Guide Revision History........................A-1 Compliance and Conformity Statements....................A-2 CE EMI Conformity Caution......................A-2 Altera Corporation...

  • Page 4: Overview

    ™ Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 5: General Description

    UG-01169 General Description 2017.09.07 • Analog: • Two MAX 10 FPGA analog-to-digital converter (ADC) SMA inputs • 2x10 ADC header • Potentiometer input to ADC • One external 16 bit digital-to-analog converter (DAC) device with SMA output • Clocking • 25 MHz single-ended, external oscillator clock source •...
  • Page 6 UG-01169 General Description 2017.09.07 Figure 1-2: MAX 10 FPGA Board Components (Bottom) Note: To determine the revision of your board, look for the serial number at the bottom of the board. QUAD SPI FLASH ENPIRION EN6337 USER DIP SWITCH (SW2)

  • Page 7: Handling The Board

    When handling the board, it is important to observe static discharge precautions. Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board. Caution: This development kit should not be operated in a Vibration Environment. Overview Altera Corporation Send Feedback...

  • Page 8: Getting Started

    Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 9: Installing The Usb-Blaster Driver

    Installation instructions for the On-Board USB-Blaster II driver for your operating system are available on the Altera website. On the Altera Programming Cable Driver Information page of the Altera website, locate the table entry for your configuration and click the link to access the instructions.
  • Page 10 This web site allows you access useful information and updated software and design examples for your board. For instructions on setting up your board to access the Board Update Portal, consult the printed Quick Start Guide that is included in the kit box. Getting Started Altera Corporation Send Feedback...

  • Page 11: Board Test System

    Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 12 ® of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applica‐ tions before attempting to reconfigure the FPGA using the Quartus II Programmer. Board Test System Altera Corporation Send Feedback...

  • Page 13: Using The Configure Menu

    Use the Configure menu to select the design you want to use. Each design example tests different board features. Choose a design from this menu and the corresponding tabs become active for testing. Figure 3-2: The Configure Menu Board Test System Altera Corporation Send Feedback...
  • Page 14 FPGA. The corresponding GUI application tabs that interface with the design are now enabled. If you use the Quartus II Programmer for configuration, rather than the Board Test System GUI, you may need to restart the GUI. Board Test System Altera Corporation Send Feedback...

  • Page 15: The System Info Tab

    The System Info tab shows the board’s current configuration. The tab displays the JTAG chain, the board’s MAC address, the Qsys memory map, and other details stored on the board. Figure 3-3: The System Info Tab Board Test System Altera Corporation Send Feedback...
  • Page 16 Indicates the Ethernet B MAC address of the board. JTAG Chain Shows all the devices currently in the JTAG chain. Qsys Memory Map Shows the memory map of the Qsys system on your board. Board Test System Altera Corporation Send Feedback...

  • Page 17: The Gpio Tab

    Table 3-2: Controls on the GPIO Tab User DIP Switch Displays the current positions of the switches in the user DIP switch banks. Change the switches on the board to see the graphical display change accordingly. Board Test System Altera Corporation Send Feedback...
  • Page 18 All button. Push Button Switches Read-only control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly. Board Test System Altera Corporation Send Feedback...

  • Page 19: The Flash Tab

    Reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table. Board Test System Altera Corporation Send Feedback...
  • Page 20 512 K test system scratch page. Random Test Starts a random data pattern test to flash memory, limited to the 512 K test system scratch page. Flash Memory Map Displays the flash memory map for the development board. Board Test System Altera Corporation Send Feedback...

  • Page 21: The Hsmc Tab

    Pattern sync: Shows the pattern synced or not synced state. The Status pattern is considered synced when the start of the data sequence is detected. CMOS: The CMOS port is available for tests. Port Board Test System Altera Corporation Send Feedback...
  • Page 22 • Clear: Resets the Detected errors and Inserted errors counters to zeroes. Test Control • Stop: Resets the test. • Number of bits tested: Displays the number of bits tested since the last reset. Board Test System Altera Corporation Send Feedback...

  • Page 23: The Ddr3 Tab

    UG-01169 3-13 The DDR3 Tab 2017.09.07 The DDR3 Tab The DDR3 Tab allows you to test the DDR3 by reading and writing to a selected amount of addresses. Figure 3-7: The DDR3 Tab Board Test System Altera Corporation Send Feedback...
  • Page 24 • Clear—Resets the Detected errors and Inserted errors counters to zeroes. Number of Addresses to Write Determines the number of addresses to use in each iteration of reads and Read and writes. Board Test System Altera Corporation Send Feedback...

  • Page 25: The Adc Tab

    The ADC Tab (analog-to-digital) shows the real-time voltage values of all of the ADC input channels. Figure 3-8: The ADC Tab The two tables displayed on this tab, ADC 1 and ADC 2 are not editable. The following table shows where the channels connect to. Board Test System Altera Corporation Send Feedback...
  • Page 26 Channel4 ADC1_CH4(J20.11) Channel5 ADC1_CH4(J20.13) Channel6 ADC1_CH6(J20.15 or POT1) Channel7 ADC1_CH7(J20.17) Dedicated Channel SMA Connector ADC 2 ANAIN2_SMA(J19) Channel0 ADC1_CH0(J20.2) Channel1 ADC1_CH1(J20.4) Channel2 ADC1_CH2(J20.6) Channel3 ADC1_CH2(J20.8) Channel4 ADC1_CH4(J20.12) Channel5 ADC1_CH4(J20.14) Channel6 ADC1_CH6(J20.16) Channel7 ADC1_CH7(J20.18) Board Test System Altera Corporation Send Feedback...

  • Page 27: The Hdmi Tab

    If you select the Start button, the TX pattern displays immediately. When you click this button, the selected TX pattern (from Color Bar) Start displays. Board Test System Altera Corporation Send Feedback...

  • Page 28: The Sleep Mode Tab

    Figure 3-10: The Sleep Mode Tab (Cropped View) Control Description running (/sleeping) This control displays the mode status as sleeping or running. It is not interactive. Note This control displays board LED events related to the sleep mode. Board Test System Altera Corporation Send Feedback...
  • Page 29 UG-01169 3-19 The Sleep Mode Tab 2017.09.07 Related Information MAX 10 Power Management User Guide Provides details on the sleep mode. Board Test System Altera Corporation Send Feedback...

  • Page 30: The Power Monitor

    Single Chart Mode allows you to choose how you want the panes to display. You can show only a single large pane, if needed. Voltage Single-Ended shows the voltage value of each power rail: Board Test System Altera Corporation Send Feedback...
  • Page 31 The LT2990 also shows a differential voltage value of the sampling resistor SENSE_P and SENSE_N. Sample Speed allows you to select Slow at 5 seconds, or Fast: at 1 second (default). Record Log saves a comma-separated values (CSV) format file in the ltc2990.csv *\examples\ directory. board_test_system Board Test System Altera Corporation Send Feedback...

  • Page 32: The Clock Control

    2017.09.07 The Clock Control The MAX 10 FPGA development board Clock Control application sets the programmable oscillators to any frequency between 10 MHz and 810 MHz. The frequencies support eight digits of precision to the right of the decimal point.
  • Page 33 Target frequency control for the programmable oscillators. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies. Figure 3-13: The Si5338 Tab...
  • Page 34 CLK0 to CLK3 controls. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies. Note: Changing CLK0 of Si5338 will affect the Clock/Power GUI.

  • Page 35: Board Components

    FPGA. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 36 2x10 header. DIP configuration and user SW2 Includes switches to control boot switch images, JTAG bypass and HSMC bypass. Jumper for the MAX 10 ADC Connects potentiometer for providing adjustable voltage to the ADC. push button Emulates pulsing the...

  • Page 37: Featured Device

    Switch to power on or off the board when power is supplied from the DC input jack. Featured Device The MAX 10 FPGA development board features the MAX 10 10M50DAF484C6GES device (U1) in a 484- pin FineLine BGA package. Table 4-2: MAX 10 FPGA 10M50DAF484C6GES Features...

  • Page 38: Configuration

    Flash Memory (CFM) and User Flash Memory (UFM) by using a download cable with the Quartus II software programmer. Selecting the Internal Configuration Scheme For all MAX 10 devices, except 10M02 device, there are total of 5 different modes you can select internal configuration. The internal configuration scheme needs to be selected before design compilation.

  • Page 39: Switch And Jumper Settings

    8. Turn on Generate compressed bitstreams if needed, and click OK. Switch and Jumper Settings This topic is for the MAX 10 FPGA development kit. This topic shows you how to restore the default factory settings and explains their functions.
  • Page 40 CONFIG_SEL (for CONFIG_SEL pin is set to high, the first boot Rev. C board) image is CFM1 or CFM2 image. This pin is read before user mode and before the nSTATUS pin is asserted. Board Components Altera Corporation Send Feedback...

  • Page 41: Status Elements

    JTAG master). When it is set to low, HSMC is bypassed. Status Elements This topic lists the non-user status elements for the MAX 10 FPGA development board. Table 4-4: General LED Signal Names Board Reference Signal Name Description —...

  • Page 42: Setup Elements

    Number PULSE_NCONFIG 3.3 V CPU_RESETn 3.3 V General User Input/Output User-defined I/O signal names, FPGA pin numbers, and I/O standards for the MAX 10 FPGA development board. Table 4-8: User-Defined Push Button Signal Names Board Reference Signal Name I/O Standard...

  • Page 43: Clock Circuitry

    1.5 V USER_LED4 AA22 1.5 V For a MAX 10 Development Kit Baseline Pinout design vist the Altera Design Store. Related Information Altera Design Store (MAX 10 Development Kit) Clock Circuitry The development board includes a four channel programmable oscillator with default frequency of 25- MHz, 50-MHz, 100-MHz, 125-MHz.

  • Page 44: On-Board Oscillators

    UG-01169 4-10 On-Board Oscillators 2017.09.07 On-Board Oscillators Figure 4-3: MAX 10 FPGA Development Board Clocks Cypress USB_CLK FA‐128 MAX II CY7C68013A 24MHz XTAL USB Blaster USB Controller 50M_MAXII USB_CLK 8Y‐25MHz Default 50 MHz XTAL 25M_ENET 10/100/1000 Base – T Default 25 MHz CH1...

  • Page 45: Off-Board Clock Input/Output

    Note: For signal CLK_50_MAXII, the output side voltage is 2.5V and the input side voltage is 3.3V. However, they are compatible electrically. Note: For signals CLK_DDR3_100_P and CLK_DDR3_100_N, at the MAX 10 input side, Differential SSTL-15 is used as I/O standard because this bank's VCCIO is 1.5V.

  • Page 46: Components And Interfaces

    MAX 10 FPGA device. 10/100/1000 Ethernet PHY The MAX 10 FFPGA development kit supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. Table 4-14: Ethernet PHY A Pin Assignments, Signal Names and Functions...
  • Page 47 UG-01169 4-13 10/100/1000 Ethernet PHY 2017.09.07 Board Reference Schematic Signal Max 10 FPGA Pin I/O Standard Description (U9) Name Number U9.94 ENETA_RX_DV 2.5V CMOS RGMII RX valid U9.3 ENETA_RX_ER 2.5V CMOS MII RX error U9.28 ENETA_RESETN 2.5V CMOS Device reset U9.23...
  • Page 48 UG-01169 4-14 10/100/1000 Ethernet PHY 2017.09.07 Table 4-15: Ethernet PHY B Pin Assignments, Signal Names and Functions Board Reference Schematic Signal Max 10 FPGA Pin I/O Standard Description (U10) Name Number U10.8 ENETB_GTX_CLK 2.5V CMOS 125 MHz RGMII TX clock U10.4...

  • Page 49: Digital-To-Analog Converter

    — 2.5V CMOS Digital-to-Analog Converter The MAX 10 FPGA comes wtih one external 16 bit digital-to-analog converter (DAC) device with an SMA output. The MAX 10 FPGA has two 12-bit successive approximation register (SAR) ADCs with sample rate of 1 MSps.

  • Page 50: Hdmi Video Output

    The transmitter incorporates HDMI v1.4 features, and is capable of supporting an input data rate up to 165 MHz (1080p @60Hz, UXGA @60Hz). The connection between HDMI transmitter and MAX 10 is established in Bank 7, and the communication can be done via I C interface.

  • Page 51: Hsmc

    QTH/QSH family of connectors. It is designed to support a full SPI-4.2 interface (17 LVDS channels) and 3 input and output clocks as well as SMBus and JTAG signals. Since MAX 10 does not have transceiver channels, the HSMC clock-data-recovery channels are left unconnected.
  • Page 52 Data bus LVDS TX channels-p HSMC_RX_D_P1 2.5V CMOS inout or Data bus LVDS RX channels-p MAX 10 doesn't have internal termination for LVDS RX. Install a 100-ohm resistor to support LVDS RX on HSMC. Board Components Altera Corporation Send Feedback...
  • Page 53 UG-01169 4-19 HSMC 2017.09.07 Board Reference (J2) Schematic Signal MAX 10 / MAX II Pin I/O Standard Description Name Number HSMC_TX_D_N1 2.5V CMOS inout or Data bus LVDS TX channels-n HSMC_RX_D_N1 2.5V CMOS inout or Data bus LVDS RX channels-n HSMC_TX_D_P2 2.5v CMOS inout or...
  • Page 54 UG-01169 4-20 HSMC 2017.09.07 Board Reference (J2) Schematic Signal MAX 10 / MAX II Pin I/O Standard Description Name Number HSMC_TX_D_N6 2.5V CMOS inout or Data bus LVDS TX channels-n HSMC_RX_D_N6 2.5V CMOS inout or Data bus LVDS RX channels-n HSMC_TX_D_P7 2.5v CMOS inout or...
  • Page 55 UG-01169 4-21 HSMC 2017.09.07 Board Reference (J2) Schematic Signal MAX 10 / MAX II Pin I/O Standard Description Name Number HSMC_TX_D_N10 2.5V CMOS inout or Data bus LVDS TX channels-n HSMC_RX_D_ AA15 2.5V CMOS inout or Data bus LVDS RX channels-n HSMC_TX_D_P11 2.5v CMOS inout or...

  • Page 56: Pmod Connectors

    Present Related Information High Speed Mezzanine Card (HSMC) Specification Pmod Connectors The MAX 10 FPGA development kit features two Digilent Pmod compatible headers, which are used to ™ connect low frequency, low I/O pin count peripheral modules. The 12-pin version Pmod connector used in this kit provides 8 I/O signal pins. The peripheral module interface also encompasses a variant using I C interface, and two or four wire MTE cables.

  • Page 57: Usb To Uart

    UG-01169 4-23 USB to UART 2017.09.07 Schematic Signal Schematic Share Bus MAX 10 FPGA Pin I/O Standard Description Name Signal Name Number PMODA_D4 PMODA_IO4 3.3V In/Out PMODA_D5 PMODA_IO5 3.3V In/Out PMODA_D6 PMODA_IO6 3.3V In/Out PMODA_D7 PMODA_IO7 3.3V In/Out — —...

  • Page 58: Memory

    Refer to the General Description section for an image of the back board. The MAX 10 FPGA provides full-speed support to a x16 DDR3 300-MHz interface by using a 1 Gbit x16 memory. Additionally, the MAX 10 supports the error correction code (ECC) feature.
  • Page 59 UG-01169 4-25 DDR3 Rev. B Board 2017.09.07 Board Reference (U5 Schematic Signal MAX 10 FPGA Pin I/O Standard Description & U6) Name Number U5.R2 -U6.M2 DDR3_A7 1.5V SSTL Address bus Caution Refer to statement above. U5.T8 - U6.N8 DDR3_A8 1.5V SSTL Address bus U5.R3 - U6.M3...

  • Page 60: Ddr3 Rev. C Board

    UG-01169 4-26 DDR3 Rev. C Board 2017.09.07 Board Reference (U5 Schematic Signal MAX 10 FPGA Pin I/O Standard Description & U6) Name Number U5.A7 DDR3_DQ12 1.5V SSTL Data bus byte lane 1 U5.A2 DDR3_DQ13 1.5V SSTL Data bus byte lane 1 U5.B8...
  • Page 61 DDR3 Rev. C Board 2017.09.07 The MAX 10 FPGA provides full-speed support to a x16 DDR3 300-MHz interface by using a 1 Gbit x16 memory. Additionally, the MAX 10 supports the error correction code (ECC) feature. Table 4-23: DDR3 Pin Assignments, Signal Names, and Functions...
  • Page 62 UG-01169 4-28 DDR3 Rev. C Board 2017.09.07 Board Reference (U5 Schematic Signal MAX 10 FPGA Pin I/O Standard Description & U6) Name Number U5.F8 DDR3_DQ3 1.5V SSTL Data bus byte lane 0 U5.H3 DDR3_DQ4 1.5V SSTL Data bus byte lane 0 U5.H8...

  • Page 63: Flash

    ZQ impedance calibration Flash The MAX 10 FPGA development kit provides a 512-Mb (megabit) quad SPI flash memory. Altera Generic QUAD SPI controller core is used by default to erase, read, and write quad SPI flash in reference designs of the Board Test System (BTS) installer.
  • Page 64 UG-01169 4-30 Flash 2017.09.07 Board Reference (U7) Schematic Signal Max 10 FPGA Pin I/O Standard Description Name Number U7.9 QSPI_IO2 3.3V Address bus U7.1 QSPI_IO3 3.3V Address bus Board Components Altera Corporation Send Feedback...

  • Page 65: Power Distribution System

    Power Distribution System 2017.09.07 Power Distribution System This topic shows the power tree drawing for the MAX 10 FPGA development board. Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels. Figure 4-4: Power Distribution System...

  • Page 66: Additional Information

    Initial release. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 67: Compliance And Conformity Statements

    (EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user. Additional Information Altera Corporation Send Feedback...

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