Building And Programming Configuration Images; Configuration Via Jtag - Alpha Data ADM-PCIE-9V3 User Manual

ADM-PCIE-9V3 User Manual
The image loaded can also support tandem PROM or tandem PCIE with field update configuration methods.
These options reduce power-on load times to help meet the PCIe reset timing requirements. Tandem with field
also enables a host system to reconfigure the user FPGA logic without losing the PCIe link, a useful feature
when system resets and power cycles are not an option.
The Alpha Data System Monitor is also capable of reconfiguring the flash memory and reprograming the FPGA.
This provides a useful failsafe mechanism to re-program the FPGA even if it drops off the PCIe bus. The system
monitor can be accessed over USB at the front panel and rear edge, or over the SMBUS connections on the
PCIe edge.

3.9.1.1 Building and Programming Configuration Images

Generate a bitfile with these constraints (see xapp1233):
• set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]
• set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
• set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
• set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
• set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
• set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
• set_property CFGBVS GND [ current_design ]
• set_property CONFIG_VOLTAGE 1.8 [ current_design ]
• set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
Generate an MCS file with these properties (write_cfgmem):
• -format MCS
• -size 64
• -interface SPIx8
• -loadbit "up 0x0000000 <directory/to/file/filename.bit>" (0th location)
• -loadbit "up 0x2000000 <directory/to/file/filename.bit>" (1st location, optional)
Program with vivado hardware manager with these settings (see xapp1233):
• SPI part: mt25qu256-spi-x1_x2_x4_x8
• State of non-config mem I/O pins: Pull-none
• Target the four files generated from the write_cfgmem tcl command.

3.9.2 Configuration via JTAG

A micro-USB AB Cable may be attached to the front panel or rear edge USB port. This permits the FPGA to be
reconfigured using the Xilinx Vivado Hardware Manager via the integrated Digilent JTAG converter box. The
device will be automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see "Using a Vivado Hardware Manager to Program an FPGA Device"
section of Xilinx UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/
ug908-vivado-programming-debugging.pdf
Functional Description
ad-ug-1322_v2_7.pdf
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