Usb Interface; Configuration; Configuration From Flash Memory; Figure 13 Flash Address Map - Alpha Data ADM-PCIE-9V3 User Manual

3.8 USB Interface

For convenience the FPGA can be configured directly from the USB connection on either the front panel or the
rear card edge (rear edge in rev7, sn306 and newer). The ADM-PCIE-9V3 utilizes the Digilent USB-JTAG
converter box which is supported by the Xilinx software tool suite. Simply connect a micro-USB AB type cable
between the ADM-PCIE-9V3 USB port and a host computer with Vivado installed. Vivado Hardware Manager will
automatically recognize the FPGA and allow you to configure the FPGA and the SBPI configuration PROM.
The same USB connector is used to directly access the system monitor system. All voltages, currents,
temperatures, and non-volatile clock configuration settings can be accessed using Alpha Data's avr2util software
at this interface.
Avr2util and associated windows USB driver is downloadable here:
ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/
Use "avr2util.exe /?" to see all options.
For example "avr2util.exe /usbcom com4 display-sensors" will desiplay all sensor values.
For example "avr2util.exe /usbcom com4 setclknv 0 156250000" will set the QSFP clock to 156.25MHz. setclk
index 1 = CAPI, index 2 = Memory, index 3 = Fabric.
Change 'com4' to match the com port number assigned under windows device manager.

3.9 Configuration

There are two main ways of configuring the FPGA on the ADM-PCIE-9V3:
• From Flash memory, at power-on, as described in
• Using USB cable connected at either USB port

3.9.1 Configuration From Flash Memory

The FPGA can be automatically configured at power-on from two 256 Mbit QSPI flash memory device configured
as an x8 SPI device (Micron part numbers MT25QU256ABA8E12-1SIT). These flash devices are typically
divided into two regions of 32 MiByte each, where each region is sufficiently large to hold an uncompressed
bitstream for a VU3P FPGA.
The ADM-PCIE-9V3 is shipped with a simple PCIe endpoint bitstream containing a basic Alpha Data ADXDMA
bitstream. Alpha Data can load in other custom bitstreams during production test, please contact
sales@alpha-data.com for more details.
It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface and
the Fallback MultiBoot are discussed in detail in Xilinx UG570.
The flash address map is as detailed below:
At power-on, the FPGA attempts to configure itself automatically in serial master mode based on the contents of
the header in the programing file. Multibook and ICAP can be used to selected between the two configuration
regions to be loaded into the FPGA. See Xilinx UG570 MultiBoot for details.
Page 16
Section 3.9.1
Section 3.9.2
Start Address (Bytes)
0x000_0000
Region 0
Default
(32 MiB)
0x200_0000
Region 1
Multi-boot
(32 MiB)
Figure 13 : Flash Address Map
ADM-PCIE-9V3 User Manual
Functional Description
ad-ug-1322_v2_7.pdf