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Alpha Data ADM-VPX3-9Z2 User Manual

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ADM-VPX3-9Z2
User Manual
Document Revision: 1.1
16th January 2020

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Summary of Contents for Alpha Data ADM-VPX3-9Z2

  • Page 1 ADM-VPX3-9Z2 User Manual Document Revision: 1.1 16th January 2020...
  • Page 2 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 © 2020 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Table Of Contents Introduction ............................1 Key Features ..........................1 References & Specifications ......................1 Order Code ............................ 2 Installation ............................3 Handling Instructions ........................3 Hardware Installation ........................3 2.2.1 System Requirements ....................... 3 2.2.2...
  • Page 4 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.10 FMC Interface and Front-Panel I/O ..................... 19 Appendix A P1 Pin Assignments ........................21 Data Plane (P1 Wafers 1-4) ......................21 Data/Expansion Plane (P1 Wafers 5-8) ..................21 Expansion/User Plane (P1 Wafers 9-14) ..................22 Control Plane (P1 Wafers 15-16) ....................
  • Page 5 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 List of Figures Figure 1 ADM-VPX3-9Z2 Air Cooled ....................... 4 Figure 2 ADM-VPX3-9Z2 Block Diagram ......................5 Figure 3 LED Locations ........................... 7 Figure 4 JTAG Boundary Scan Chain ......................10 Figure 5 Clocks ..............................
  • Page 6 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Page Intentionally left blank...

  • Page 7: Introduction

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 1 Introduction The ADM-VPX3-9Z2 shall be a high performance reconfigurable 3U OpenVPX format board based on the Xilinx Zynq Ultrascale+ range of Multiprocessor System-on-Chips (MPSoC). 1.1 Key Features Key Features • 3U Open VPX, compliant to VITA Standard 46.0 and 65 •...

  • Page 8: Order Code

    /AC1 = air cooled industrial /CC1 = conduction cooled industrial blank= No optics fitted , Optics /O = V66.4 Optics fitted Table 2 : Build Options Not all combinations are available. Please check with Alpha Data sales for details. Page 2 Introduction ad-ug-1323_v1_1.pdf...

  • Page 9: Installation

    2.2.1 System Requirements The ADM-VPX3-9Z2 is a 3U OpenVPX compliant FPGA card with FMC front IO interface. Alpha Data offers a Rear Transition Module (RTM) that breaks out all P2 IO and P1 control lanes (Part number: ADM-VPX3-9Z2-RTM). 2.2.2 Cooling Requirements The power dissipation of the board is highly dependent on the FPGA application.

  • Page 10: Software Installation

    Figure 1 : ADM-VPX3-9Z2 Air Cooled 2.3 Software Installation Please refer to the Reference Designs on the Alpha Data Download Site. Example projects for configuring the Zynq Ultrascale+ MPSOC device and example software for running on the ARM CPUs can be downloaded from there.

  • Page 11: Functional Description

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3 Functional Description 3.1 Overview Figure 2 : ADM-VPX3-9Z2 Block Diagram Functional Description Page 5 ad-ug-1323_v1_1.pdf...

  • Page 12: Switch Definitions

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.1.1 Switch Definitions There are two push-button reset switches on the board. Their functions are detailed below. Switch Ref. Function ON State Off State Hardware Hardware Reset (complete restart) Normal Operation Reset...

  • Page 13: Led Definitions

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.1.2 LED Definitions There are seven LEDs to provide a visual indication of the board status. Their locations are shown in Figure 3 D10 D8 D9 D15 D14 Figure 3 : LED Locations...

  • Page 14: Table 6 Main Led Definitions

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Comp. Ref. Function ON State Off State System Monitor D13 (Green) Table 26 Status System Monitor D18 (Red) Table 26 Status FPGA (PL) D15 (Green) PL is configured PL is not configured...

  • Page 15: Vpx P0 Interface

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.2 VPX P0 Interface 3.2.1 SYSRESET# VPX Reset In. This signal is an active low input from the system. When asserted, the PS PCIe interface will be reset. The SYSRESET# signal is translated to 1.8V levels and connected to the FPGA at MIO pin J22.

  • Page 16: Jtag Interface

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.4 JTAG Interface 3.4.1 On-board Interface A JTAG boundary scan chain is connected to header J2. This allows the connection of the Xilinx JTAG cable. The scan chain is shown in Figure JTAG Boundary Scan...

  • Page 17: Clocks

    FMC+ connector, the board has 2 user-programmable clock generators. These clocks can be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols. A complete overview of the clock routing on the ADM-VPX3-9Z2 is given in Clocks. A description of each clock follows.

  • Page 18: Io Delay Reference Clock (Fabric_Clk)

    There are two programable clock sources that are forwarded throughout the FPGA. These clocks can be programmed via the avr2util utility contained within the Alpha Data ADM-VPX3-9Z2 SDK. PROGCLK1 and PROGCLK2 are generated by a dedicated programmable clock generator IC and offer extremely high frequency resolutions (1ppm increments).

  • Page 19: Module To Carrier Global Clocks (Clk_M2C)

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.5.4 Module to Carrier Global Clocks (CLK_M2C) A connected FMC+ board can generate a number of differential Global clocks (as per the FMC standard). They each connect to an global clock input on the FPGA.

  • Page 20: Usb_Refclk24M

    The memory devices attached to the PS side of the MPSoC are outlined below. 3.7.2.1 Quad SPI Flash Memory The ADM-VPX3-9Z2 has two Quad SPI Flash devices, up to 2Gb each. They can be interfaced seperately in x1, x2,x4 modes or together in x8 mode.

  • Page 21: Microsd And Emmc Flash Memories

    V1.1 - 16th January 2020 3.7.2.2 MicroSD and eMMC Flash Memories The ADM-VPX3-9Z2 can interface to either a MicroSD card (SD 2.0 standard at 3.3V) or an eMMC device (v4.5 at 1.8V). The Switch SW4-7 determines which of the two interfaces is in use (as they share common MIO pins).

  • Page 22: Usb Interfaces

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.7.5 USB Interfaces The 9Z2 has three external USB interfaces. Interfaces USB1 and USB2 are connected between VPX P1 connector and the PS side of the MPSoC. The PS acts as the USB host to interfaces USB1 and USB2.

  • Page 23: Fmc+ Gpio Interface

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 3.8.3 FMC+ GPIO Interface The FMC+ Connector (J1) has GPIO connections arranged as follows: FPGA Group Name Function Bank LA(12:2) 11 diff. Pairs / 22 single-ended LA_0 LA_CC (1:0) 2x Regional Clocks / GPIO pairs / 4 single-ended LA(33:19) 15 diff.

  • Page 24: Automatic Temperature Monitoring

    FPGA on-die temperature (measured in TMP422) Table 24 : Voltage and Temperature Monitors (in microcontroller) The system monitor sensor values can be read via usb using the avr2util utility contained within the Alpha Data ADM-VPX3-9Z2 SDK. 3.9.1 Automatic Temperature Monitoring The system monitor checks that the board and FPGA are being operated within the specified limits.

  • Page 25: Fmc Interface And Front-Panel I/O

    The FMC+ interface provides a high-performance and flexible front-panel interface through a range of interchangeable, industry standard IO modules which connect at receptacle J1. The FMC+ interface adheres to VITA 57.4. The ADM-VPX3-9Z2 utilizes all possible FMC+ connectivity. This includes all GPIO, all MGT links, and all clock capable IO.
  • Page 26 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Page Intentionally left blank Page 20 Functional Description ad-ug-1323_v1_1.pdf...

  • Page 27: Appendix A P1 Pin Assignments

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Appendix A: P1 Pin Assignments Appendix A.1: Data Plane (P1 Wafers 1-4) Signal VPX P1 FPGA FPGA VPX P1 Signal PCIE_TX0_P AB29 AB33 PCIE_RX0_P PCIE_TX0_N AB30 AB34 PCIE_RX0_N PCIE_TX1_P AA31 PCIE_RX1_P PCIE_TX1_N...

  • Page 28: Expansion/User Plane (P1 Wafers 9-14)

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Appendix A.3: Expansion/User Plane (P1 Wafers 9-14) Signal VPX P1 FPGA FPGA VPX P1 Signal P1_TX1_P AB29 AB33 P1_RX1_P P1_TX1_N AB30 AB34 P1_RX1_N P1_TX2_P P1_RX2_P P1_TX2_N P1_RX2_N P1_TX3_P P1_RX3_P P1_TX3_N P1_RX3_N P1_MUX_TX_P_2...

  • Page 29: Appendix B P2 Pin Assignments

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Appendix B: P2 Pin Assignments Appendix B.1: GPIO (P2 Wafers 4-6) Signal VPX P2 FPGA FPGA VPX P2 Signal GP1_N GP7_N GP1_P GP7_P GP2_N GP8_N GP2_P GP8_P GP3_N GP9_N GP3_P GP9_P GP4_N...

  • Page 30: Appendix C Fmc Pin Assignments

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Appendix C: FMC Pin Assignments Appendix C.1: GPIO Pins Signal FMC (J1) FPGA FPGA FMC (J1) Signal LA00_CC_N HA00_CC_N LA00_CC_P HA00_CC_P LA01_CC_N HA01_CC_N LA01_CC_P HA01_CC_P LA02_N HA02_N LA02_P HA02_P LA03_N HA03_N LA03_P...
  • Page 31 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Signal FMC (J1) FPGA FPGA FMC (J1) Signal LA15_P HA15_P LA16_N AA10 HA16_N LA16_P AA11 HA16_P LA17_CC_N HA17_CC_N LA17_CC_P HA17_CC_P LA18_CC_N HA18_N LA18_CC_P HA18_P LA19_N HA19_N LA19_P AD10 HA19_P LA20_N AF12 HA20_N...

  • Page 32: Clock Pins

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Signal FMC (J1) FPGA FPGA FMC (J1) Signal LA33_P HB09_P HB16_N HB10_N HB16_P HB10_P HB17_CC_N HB11_N HB17_CC_P HB11_P HB18_N HB12_N HB18_P HB12_P HB19_N HB13_N HB19_P HB13_P HB20_N HB14_N HB20_P HB14_P HB21_N HB15_N...

  • Page 33: Mgt Pins

    ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Appendix C.3: MGT Pins Signal FMC (J1) FPGA FPGA FMC (J1) Signal DP0_M2C_N DP0_C2M_N DP0_M2C_P DP0_C2M_P DP1_M2C_N DP1_C2M_N DP1_M2C_P DP1_C2M_P DP2_M2C_N DP2_C2M_N DP2_M2C_P DP2_C2M_P DP3_M2C_N DP3_C2M_N DP3_M2C_P DP3_C2M_P DP4_M2C_N DP4_C2M_N DP4_M2C_P DP4_C2M_P...
  • Page 34 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Signal FMC (J1) FPGA FPGA FMC (J1) Signal DP17_M2C_N DP17_C2M_N DP17_M2C_P DP17_C2M_P DP18_M2C_N DP18_C2M_N DP18_M2C_P DP18_C2M_P DP19_M2C_N DP19_C2M_N DP19_M2C_P DP19_C2M_P DP20_M2C_N DP20_C2M_N DP20_M2C_P DP20_C2M_P DP21_M2C_N DP21_C2M_N DP21_M2C_P DP21_C2M_P DP22_M2C_N DP22_C2M_N DP22_M2C_P DP22_C2M_P...
  • Page 35 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Revision History Date Revision Nature of Change Initial Draft 21 Sep 2018 First Release 02 Jan 2020 Added pinout tables 16 Jan 2020 Revision Table Page 29 ad-ug-1323_v1_1.pdf...
  • Page 36 ADM-VPX3-9Z2 User Manual V1.1 - 16th January 2020 Page Intentionally left blank Address: Suite L4A, 160 Dundee Street, Address: 611 Corporate Circle, Suite H Edinburgh, EH11 1DQ, UK Golden, CO 80401 Telephone: +44 131 558 2600 Telephone: (303) 954 8768...

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