Programming Clock (Emcclk); Qsfp28; Table 6 Fabric Clock; Table 7 Emcclk - Alpha Data ADM-PCIE-9V3 User Manual

ADM-PCIE-9V3 User Manual
FABRIC_CLK
DIFF_TERM_ADV = TERM_100 is required for LVDS termination

3.2.3 Programming Clock (EMCCLK)

An 100MHz clock is fed into the EMCCLK pin to drive the SPI flash device during configuration of the FPGA.
Note that this is not a global clock capable IO pin.
REFCLK100M

3.2.4 QSFP28

The QSFP28 cages are located in MGT quads 127 and 128 and use a 161.1328125MHz default reference clock.
Note that this clock frequency can be changed to any arbitrary clock frequency up to 312MHz by re-programing
the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or
over USB with the appropriate Alpha Data Software tools.
GTY_CLK_0B
GTY_CLK_0C
The QSFP28 cages are also located such that they can be clocked from a Si5328 jitter attenuator clock
multiplier. If jitter attenuation is required please see the reference documentation for the Si5328. https://
www.silabs.com/Support%20Documents/TechnicalDocs/Si5328.pdf
The Si5328 is configured with a 114.285MHz oscilator on XA and XB
The Si5328 SDA pin connects at FPGA pin L29 (1.8V), SCL is at FPGA pin L30 (1.8V) with external pull-ups
included.
The Si5328 can be reached at I2C address 1101000
The Si5328 input clock comes from FPGA pins M29 and M30, and includes 100 Ohm differential termination and
100nF AC coupled termination from the 1.8V FPGA bank suitable for LVDS signal levels.
The Si5328 output clocks are AC coupled with 10nF capacitors and then connected to the FPGA MGTREFCLK
pins shown in the table below. LVDS signal standard is recommended on these nets as well.
SI5328_REFCLK_OUT0
SI5328_REFCLK_OUT1
Functional Description
ad-ug-1322_v2_7.pdf
Signal Target FPGA Input
IO_L12P_T1U_GC_64
Signal
IO_L24P_T3U_N10_EMCCLK_65
Signal Target FPGA Input
MGTREFCLK0_128
MGTREFCLK0_127
Table 8 : QSFP28 Reference Clocks
Signal Target FPGA Input
MGTREFCLK1_128
MGTREFCLK1_127
Table 9 : QSFP28 Jitter Attenuated Reference Clocks
I/O Standard
Table 6 : Fabric Clock
Target FPGA Input
Table 7 : EMCCLK
I/O Standard
I/O Standard
"P" pin
LVDS AP26
I/O Standard
LVCMOS18
"P" pin
LVDS N33
LVDS U33
"P" pin
LVDS L33
LVDS R33
"N" pin
AP27
pin
AJ28
"N" pin
N34
U34
"N" pin
L34
R34
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