3.1.1 Switches
The ADM-PCIE-9V3 has a quad DIP switch SW1, located on the rear side of the board. The function of each
switch in SW1 is detailed below:
Switch
SW1-1
SW1-2
SW1-3
SW1-4
SW2-1
SW2-2
SW2-3
SW2-4
Use IO Standard "LVCMOS18" when constraining the user switch pin.
Page 6
Factory
Function
Default
User
OFF
Switch 0
User
OFF
Switch 1
Service
OFF
Mode
JTAG
OFF
Source
HOST_I2
ON
C_EN
CAPI_VP
ON
D_EN
CAPI_VP
ON
D_WP
ON
Reserved
Figure 6 : Switches
OFF State
Pin AV27 = '1'
Pin AW27 = '1'
Regular Operation
JTAG to FPGA from USB
Sysmon over PCIe I2C
OpenCAPI VPD available
CAPI VPD is write protected
Reserved
Table 3 : Switch Functions
ADM-PCIE-9V3 User Manual
ON State
Pin AV27 = '0'
Pin AW27 = '0'
Firmware update service mode
JTAG to FPGA from debug
header
Sysmon isolated
OpenCAPI VPD isolated
CAPI VPD is writable
Reserved
Functional Description
ad-ug-1322_v2_7.pdf
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