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Alpha Data ADM-PCIE-9V3 User Manual

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ADM-PCIE-9V3
User Manual
Document Revision: 2.7
14th December 2018

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Summary of Contents for Alpha Data ADM-PCIE-9V3

  • Page 1 ADM-PCIE-9V3 User Manual Document Revision: 2.7 14th December 2018...
  • Page 2 ADM-PCIE-9V3 User Manual © 2018 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    ADM-PCIE-9V3 User Manual Table Of Contents Introduction ............................1 Key Features ..........................1 Order Code ............................ 1 PCB Information ..........................2 Physical Specifications ........................2 Chassis Requirements ........................2 2.2.1 PCI Express ..........................2 2.2.2 Mechanical Requirements ......................2 2.2.3 Power Requirements .........................
  • Page 4 Table 14 Status LED Definitions ........................15 Table 15 Complete Pinout Table ........................21 List of Figures Figure 1 ADM-PCIE-9V3 Product Photo ......................1 Figure 2 Thermal Performance ........................3 Figure 3 Optional Blower ..........................4 Figure 4 Full Height Heat Sink ......................... 4 Figure 5 ADM-PCIE-9V3 Block Diagram ......................

  • Page 5: Introduction

    ADM-PCIE-9V3 User Manual 1 Introduction The ADM-PCIE-9V3 is a high-performance reconfigurable computing card intended for Data Center applications, featuring a Xilinx Virtex UltraScale Plus FPGA. Figure 1 : ADM-PCIE-9V3 Product Photo 1.1 Key Features Key Features • PCIe Gen1/2/3 x1/2/4/8/16 capable •...

  • Page 6: Pcb Information

    The PCIe Specification permits a standard low-profile, half-length PCIe card to dissipate up to 25 W of power, drawn from the PCIe slot. The ADM-PCIE-9V3 may consume more than 25 W of power for larger user FPGA designs. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a power estimator tool available from Alpha Data.

  • Page 7: Thermal Performance

    The ADM-PCIE-9V3 comes with a heat sink to reduce the heat of the FPGA which is typically the hottest point on the card. The FPGA die temperature must remain under 100 degrees Celsius. To calculate the FPGA die temperature, take your application power and multiply by Theta JA from the table below, and add to your system internal ambient temperature.

  • Page 8: Optional Blower

    Because it is possible for generic PC chassis to not provide sufficient airflow to cool the FPGA, the ADM-PCIE-9V3 is shipped with an uninstalled blower. The blower is optional and can be easily installed with a Philips screw driver at the discretion of the user. Ensure the opening is facing the heatsink fins. The blower hangs off the back of the PCB outside of the PCIe card envelope.

  • Page 9: Functional Description

    3 Functional Description 3.1 Overview The ADM-PCIE-9V3 is a versatile reconfigurable computing platform with a Virtex UltraScale VU3P FPGA, a Gen3x16 PCIe interface, two banks of DDR4 both 72 bits wide (for 64 bits with 8 bits ECC), two QSFP28 cages capable of 8x 28G or 2x 112G Serial IO of any Xilinx supported standard (Ethernet, SRIO, Infiniband, etc.), one...

  • Page 10: Switches

    ADM-PCIE-9V3 User Manual 3.1.1 Switches The ADM-PCIE-9V3 has a quad DIP switch SW1, located on the rear side of the board. The function of each switch in SW1 is detailed below: Figure 6 : Switches Factory Switch Function OFF State...

  • Page 11: Leds

    ADM-PCIE-9V3 User Manual 3.1.2 LEDs There are 8 LEDs on the ADM-PCIE-9V3, 5 of which are general purpose and whose meaning can be defined by the user. The other 3 have fixed functions described below: USER_LED_G1 DONE USR_LED_R USR_LED_G0 Figure 7 : Backside LEDs...

  • Page 12: Clocking

    Any clock out of an Si5338 Clock Synthesizer is re-configurable from either the front panel USB USB Interface the Alpha Data bridge IP available in the board support package (sold separately). This allows the user to configure almost any arbitrary clock frequencies during application run time. Maximum clock frequency is 312.5MHz.

  • Page 13: Programming Clock (Emcclk)

    Note that this clock frequency can be changed to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or over USB with the appropriate Alpha Data Software tools.

  • Page 14: Ultraport Slimsas

    Note that this clock frequency can be changed to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or over USB with the appropriate Alpha Data Software tools. Signal...

  • Page 15: Pci Express

    ADM-PCIE-9V3 SDK. All constraint information is included in Complete Pinout Table. Alpha Data has also provided a custom csv timing file for use with Xilinx MIG. This can be downloaded from the ADM-PCIE-9V3 product page.

  • Page 16: Qsfp28

    The LP_MODE (Low Power Mode) to each QSFP28 cage is tied to ground. Figure 11 : QSFP Locations The order options for the ADM-PCIE-9V3 include an option to fit the QSFP28 optical transceivers. The table below shows the part number for the transceivers fitted with each option.

  • Page 17: Opencapi Ultraport Slimsas

    ADM-PCIE-9V3 User Manual 3.6 OpenCAPI Ultraport SlimSAS An Ultraport SlimSAS receptacles along the top of the board allows for OpenCAPI compliant interfaces running at 200G (8 chanels at 25G). Please contact support@alpha-data.com or your IBM representative for more details on OpenCAPI and its benefits.

  • Page 18: System Monitor

    ADM-PCIE-9V3 User Manual 3.7 System Monitor The ADM-PCIE-9V3 has the ability to monitor temperature, voltage, and current of the system to check on the operation of the board. The monitoring is implemented using an Atmel AVR microcontroller. If the core FPGA temperature exceeds 100 degrees Celsius, the FPGA will be cleared to prevent damage to the card.

  • Page 19: System Monitor Status Leds

    ADM-PCIE-9V3 User Manual 3.7.1 System Monitor Status LEDs LEDs D6 (Red) and D5 (Green) indicate the card health status. LEDs Status Green Running and no alarms Green + Red Standby (Powered off) Flashing Green + Flashing Red Attention - critical alarm active...

  • Page 20: Usb Interface

    For convenience the FPGA can be configured directly from the USB connection on either the front panel or the rear card edge (rear edge in rev7, sn306 and newer). The ADM-PCIE-9V3 utilizes the Digilent USB-JTAG converter box which is supported by the Xilinx software tool suite. Simply connect a micro-USB AB type cable between the ADM-PCIE-9V3 USB port and a host computer with Vivado installed.

  • Page 21: Building And Programming Configuration Images

    The Alpha Data System Monitor is also capable of reconfiguring the flash memory and reprograming the FPGA. This provides a useful failsafe mechanism to re-program the FPGA even if it drops off the PCIe bus. The system monitor can be accessed over USB at the front panel and rear edge, or over the SMBUS connections on the PCIe edge.

  • Page 22: Gpio Connector

    The first two pins of the GPIO connector can be used as an isolated timing input signal. Applications can either directly connect to the GPIO connector, or Alpha Data can provide a cabled solution with an SMA or similar Page 18 Functional Description ad-ug-1322_v2_7.pdf...

  • Page 23: User Eeprom

    ADM-PCIE-9V3 User Manual connector on the front panel. Contact sales@alpha-data.com for front panel connector options. For pin locations, see signal name PPS_BUF_1V8 in Complete Pinout Table. The signal is isolated through a optical isolator part number ACPL-M61L with a 739 ohm of series resistance.
  • Page 24 ADM-PCIE-9V3 User Manual Page Intentionally left blank Page 20 Functional Description ad-ug-1322_v2_7.pdf...

  • Page 25: Appendix A Complete Pinout Table

    ADM-PCIE-9V3 User Manual Appendix A: Complete Pinout Table Signal Name Bank Voltage Number AU24 AVR_B2U_1V8 AW26 AVR_HS_B2U_1V8 AV26 AVR_HS_CLK_1V8 AV24 AVR_HS_U2B_1V8 AV25 AVR_MON_CLK_1V8 AU25 AVR_U2B_1V8 AC34 CAPI_CLK_C_PIN_N MGT_REFCLK AC33 CAPI_CLK_C_PIN_P MGT_REFCLK AG34 CAPI_CLK_D_PIN_N MGT_REFCLK AG33 CAPI_CLK_D_PIN_P MGT_REFCLK CAPI_I2C_SCL_1V8 CAPI_I2C_SDA_1V8 AV37...
  • Page 26 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number AF35 CAPI_TX10_P AT36 CAPI_TX2_N AT35 CAPI_TX2_P AP36 CAPI_TX3_N AP35 CAPI_TX3_P AM36 CAPI_TX7_N AM35 CAPI_TX7_P AK36 CAPI_TX8_N AK35 CAPI_TX8_P AH36 CAPI_TX9_N AH35 CAPI_TX9_P AB10 CCLK DDR4_0_A0 DDR4_0_A1 DDR4_0_A10 DDR4_0_A11 DDR4_0_A12 DDR4_0_A13 DDR4_0_A14 DDR4_0_A15...
  • Page 27 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number DDR4_0_BG1 DDR4_0_C0 DDR4_0_C1 DDR4_0_C2 DDR4_0_CK_C DDR4_0_CK_T DDR4_0_CKE DDR4_0_CS_N DDR4_0_DM0 DDR4_0_DM1 DDR4_0_DM2 DDR4_0_DM3 DDR4_0_DM4 DDR4_0_DM5 DDR4_0_DM6 DDR4_0_DM7 DDR4_0_DM8 DDR4_0_DQ0 DDR4_0_DQ1 DDR4_0_DQ10 DDR4_0_DQ11 DDR4_0_DQ12 DDR4_0_DQ13 DDR4_0_DQ14 DDR4_0_DQ15 DDR4_0_DQ16 DDR4_0_DQ17 DDR4_0_DQ18 DDR4_0_DQ19 DDR4_0_DQ2 DDR4_0_DQ20 DDR4_0_DQ21...
  • Page 28 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number DDR4_0_DQ25 DDR4_0_DQ26 DDR4_0_DQ27 DDR4_0_DQ28 DDR4_0_DQ29 DDR4_0_DQ3 DDR4_0_DQ30 DDR4_0_DQ31 DDR4_0_DQ32 DDR4_0_DQ33 DDR4_0_DQ34 DDR4_0_DQ35 DDR4_0_DQ36 DDR4_0_DQ37 DDR4_0_DQ38 DDR4_0_DQ39 DDR4_0_DQ4 DDR4_0_DQ40 DDR4_0_DQ41 DDR4_0_DQ42 DDR4_0_DQ43 DDR4_0_DQ44 DDR4_0_DQ45 DDR4_0_DQ46 DDR4_0_DQ47 DDR4_0_DQ48 DDR4_0_DQ49 DDR4_0_DQ5 DDR4_0_DQ50 DDR4_0_DQ51 DDR4_0_DQ52 DDR4_0_DQ53...
  • Page 29 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number DDR4_0_DQ57 DDR4_0_DQ58 DDR4_0_DQ59 DDR4_0_DQ6 DDR4_0_DQ60 DDR4_0_DQ61 DDR4_0_DQ62 DDR4_0_DQ63 DDR4_0_DQ64 DDR4_0_DQ65 DDR4_0_DQ66 DDR4_0_DQ67 DDR4_0_DQ68 DDR4_0_DQ69 DDR4_0_DQ7 DDR4_0_DQ70 DDR4_0_DQ71 DDR4_0_DQ8 DDR4_0_DQ9 DDR4_0_DQS0_C DDR4_0_DQS0_T DDR4_0_DQS1_C DDR4_0_DQS1_T DDR4_0_DQS2_C DDR4_0_DQS2_T DDR4_0_DQS3_C DDR4_0_DQS3_T DDR4_0_DQS4_C DDR4_0_DQS4_T DDR4_0_DQS5_C DDR4_0_DQS5_T DDR4_0_DQS6_C...
  • Page 30 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number DDR4_0_DQS8_C DDR4_0_DQS8_T DDR4_0_ODT DDR4_0_PAR DDR4_0_RESET_N DDR4_0_TEN DDR4_1_A0 DDR4_1_A1 DDR4_1_A10 AL10 DDR4_1_A11 DDR4_1_A12 AK11 DDR4_1_A13 DDR4_1_A14 AV10 DDR4_1_A15 AT11 DDR4_1_A16 DDR4_1_A17 AP11 DDR4_1_A2 DDR4_1_A3 AT10 DDR4_1_A4 AL12 DDR4_1_A5 AM12 DDR4_1_A6 AM10 DDR4_1_A7 AL11...
  • Page 31 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number AU12 DDR4_1_CKE AT12 DDR4_1_CS_N AG12 DDR4_1_DM0 AK15 DDR4_1_DM1 AP16 DDR4_1_DM2 AV16 DDR4_1_DM3 AP21 DDR4_1_DM4 AU20 DDR4_1_DM5 AG19 DDR4_1_DM6 AL18 DDR4_1_DM7 AG14 DDR4_1_DM8 DDR4_1_DQ0 AK10 DDR4_1_DQ1 AL13 DDR4_1_DQ10 AM14 DDR4_1_DQ11 AL15 DDR4_1_DQ12 AM17...
  • Page 32 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number AW14 DDR4_1_DQ30 AW18 DDR4_1_DQ31 AP19 DDR4_1_DQ32 AT20 DDR4_1_DQ33 AN21 DDR4_1_DQ34 AR19 DDR4_1_DQ35 AN20 DDR4_1_DQ36 AR18 DDR4_1_DQ37 AR20 DDR4_1_DQ38 AP18 DDR4_1_DQ39 DDR4_1_DQ4 AW19 DDR4_1_DQ40 AU22 DDR4_1_DQ41 AV19 DDR4_1_DQ42 AW22 DDR4_1_DQ43 AU18 DDR4_1_DQ44 AT22...
  • Page 33 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number AN19 DDR4_1_DQ62 AL20 DDR4_1_DQ63 AF15 DDR4_1_DQ64 AJ17 DDR4_1_DQ65 AH17 DDR4_1_DQ66 AJ14 DDR4_1_DQ67 AG15 DDR4_1_DQ68 AJ13 DDR4_1_DQ69 AJ12 DDR4_1_DQ7 AG17 DDR4_1_DQ70 AJ16 DDR4_1_DQ71 AM15 DDR4_1_DQ8 AN14 DDR4_1_DQ9 DDR4_1_DQS0_C DDR4_1_DQS0_T AL16 DDR4_1_DQS1_C AK16 DDR4_1_DQS1_T...
  • Page 34 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number DONE_1V8 AB15 AB16 AJ28 EMCCLK_B AP27 FABRIC_CLK_PIN_N 1.8(DIFFTERM required) AP26 FABRIC_CLK_PIN_P 1.8(DIFFTERM required) AR26 FPGA_CPLD_SPARE FPGA_FLASH_CE1_L AV30 FPGA_FLASH_CE2_L FPGA_FLASH_DQ0 FPGA_FLASH_DQ1 FPGA_FLASH_DQ2 FPGA_FLASH_DQ3 AF30 FPGA_FLASH_DQ4 AG30 FPGA_FLASH_DQ5 AF28 FPGA_FLASH_DQ6 AG28 FPGA_FLASH_DQ7 AH24 FRONT_LED_0...
  • Page 35 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number AN26 MEM_CLK_1_PIN_N 1.8(Requires DIFFTERM) AN25 MEM_CLK_1_PIN_P 1.8(Requires DIFFTERM) OPTICAL_INT_1V8_L OPTICAL_RESET_1V8_L OPTICAL_SCL_1V8 OPTICAL_SDA_1V8 PCIE_REFCLK_1_PIN_N MGT_REFCLK PCIE_REFCLK_1_PIN_P MGT_REFCLK PCIE_REFCLK_2_PIN_N MGT_REFCLK PCIE_REFCLK_2_PIN_P MGT_REFCLK PCIE_RX0_N PCIE_RX0_P PCIE_RX1_N PCIE_RX1_P PCIE_RX10_N PCIE_RX10_P PCIE_RX11_N PCIE_RX11_P PCIE_RX12_N PCIE_RX12_P PCIE_RX13_N PCIE_RX13_P...
  • Page 36 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number PCIE_RX6_P PCIE_RX7_N PCIE_RX7_P PCIE_RX8_N PCIE_RX8_P PCIE_RX9_N PCIE_RX9_P PCIE_TX0_PIN_N PCIE_TX0_PIN_P PCIE_TX1_PIN_N PCIE_TX1_PIN_P PCIE_TX10_PIN_N PCIE_TX10_PIN_P PCIE_TX11_PIN_N PCIE_TX11_PIN_P PCIE_TX12_PIN_N PCIE_TX12_PIN_P PCIE_TX13_PIN_N PCIE_TX13_PIN_P PCIE_TX14_PIN_N PCIE_TX14_PIN_P PCIE_TX15_PIN_N PCIE_TX15_PIN_P PCIE_TX2_PIN_N PCIE_TX2_PIN_P PCIE_TX3_PIN_N PCIE_TX3_PIN_P PCIE_TX4_PIN_N PCIE_TX4_PIN_P PCIE_TX5_PIN_N PCIE_TX5_PIN_P PCIE_TX6_PIN_N...
  • Page 37 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number PCIE_TX8_PIN_N PCIE_TX8_PIN_P PCIE_TX9_PIN_N PCIE_TX9_PIN_P AJ31 PERST_1V8_0_L AH29 PERST_1V8_1_L POWER9_SCL_1V8 POWER9_SDA_1V8 PPS_BUF_1V8 PRE_DETECT_1V8 PROGRAM_B_1V8 PUDC_B QSFP0_MODPRS_L QSFP0_RX0_N QSFP0_RX0_P QSFP0_RX1_N QSFP0_RX1_P QSFP0_RX2_N QSFP0_RX2_P QSFP0_RX3_N QSFP0_RX3_P QSFP0_SEL_1V8_L QSFP0_TX0_N QSFP0_TX0_P QSFP0_TX1_N QSFP0_TX1_P QSFP0_TX2_N QSFP0_TX2_P QSFP0_TX3_N QSFP0_TX3_P...
  • Page 38 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number QSFP1_RX2_N QSFP1_RX2_P QSFP1_RX3_N QSFP1_RX3_P QSFP1_SEL_1V8_L QSFP1_TX0_N QSFP1_TX0_P QSFP1_TX1_N QSFP1_TX1_P QSFP1_TX2_N QSFP1_TX2_P QSFP1_TX3_N QSFP1_TX3_P REFCLK100_PIN_N REFCLK100_PIN_P SI5328_1V8_SCL SI5328_1V8_SDA SI5328_REFCLK_IN_N 1.8 (LVDS) SI5328_REFCLK_IN_P 1.8(LVDS) SI5328_REFCLK_OUT0_PIN_N MGT_REFCLK SI5328_REFCLK_OUT0_PIN_P MGT_REFCLK SI5328_REFCLK_OUT1_PIN_N MGT_REFCLK SI5328_REFCLK_OUT1_PIN_P MGT_REFCLK AT25 SPARE_SCL...
  • Page 39 ADM-PCIE-9V3 User Manual Signal Name Bank Voltage Number AW27 USR_SW1 Table 15 : Complete Pinout Table Complete Pinout Table Page 35 ad-ug-1322_v2_7.pdf...
  • Page 40 ADM-PCIE-9V3 User Manual Revision History Date Revision Changed By Nature of Change Initial Release 9 Sep 2016 K. Roth Added available power by rail table to Power Requirements, Added section: Custom Flash Write Interface, Updated 6 Jan 2017 K. Roth clock termination recommendation to HSTL_I in Clocking, Added note about PCIe RX equalization options.

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