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Summary of Contents for Alpha Data ADM-VB630
- Page 1 ADM-VB630 User Manual Document Revision: 1.0 7th Jan 2025...
- Page 2 ADM-VB630 User Manual V1.0 - 7th Jan 2025 © 2025 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.
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Page 3: Table Of Contents
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Table Of Contents Introduction ............................1 Key Features ..........................1 References & Specifications ......................1 Order Code ............................ 2 Installation ............................3 Handling Instructions ........................3 Hardware Installation ........................3 2.2.1 System Requirements ........................ 3 2.2.2... - Page 4 ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.9.1 I/O Bank Voltages ........................17 4.9.2 PL MGT Links .......................... 17 4.9.3 VPX P2 GPIO Interface ......................17 4.9.4 VPX GPIO Buffers ........................17 4.9.5 DDR4 Memory ......................... 18 4.10 System Monitoring ........................18 4.10.1...
- Page 5 Table 32 DDR4 Pinout Table .......................... 30 List of Figures Figure 1 ADM-VB630 ............................4 Figure 2 ADM-VB630 Block Diagram ....................... 7 Figure 3 LED and Switch Locations ......................... 9 Figure 4 JTAG Boundary Scan Chain ......................13 Figure 5...
- Page 6 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Page Intentionally left blank...
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Page 7: Introduction
ADM-VB630 User Manual V1.0 - 7th Jan 2025 1 Introduction The ADM-VB630 is the base board at the core of the ADK-VB630 Versal AI Edge Development Platform for Space 2.0. 1.1 Key Features Key Features • VPX 3U Form Factor •... -
Page 8: Order Code
/CC4 - build to order with Space Qualified Components /C(x) - build to order with Customer Specific Modifications Table 2 : Build Options Not all combinations may be available. Please check with Alpha Data sales for details. Page 2 Introduction... -
Page 9: Installation
The ADM-VB630 is a 3U Space VPX reference platform for the AMD Versal AI Edge XQVE2302 Adaptable SoC platform for Space 2.0. Alpha Data offers a Rear Transition Module (RTM) that breaks out all P1 and P2 IO and control lanes (Part number: ADM-VB630-RTM). -
Page 10: Software Installation
Figure 1 : ADM-VB630 2.3 Software Installation Please refer to the Reference Designs on the Alpha Data Download Site. Example projects for configuring the Versal Adaptive SoC device and example software for running on the ARM CPUs can be downloaded from there. -
Page 11: Board Information
A 3U VPX rack is required for mechanical compatibility. 3.2.2 Power Requirements The ADM-VB630 is powered via the +12V VPX power rail, all the internal power rails are generated from this rail. The ADM-VB630 is capable of drawing up to 6A on the +12V VPX power rail. -
Page 12: Thermal Performance
If the Adaptive SoC core temperature exceeds 105 degrees Celsius, the Adaptive SoC design will be cleared to prevent the card from over-heating. The power dissipation can be estimated by using the Alpha Data power estimator in conjunction with the AMD Power Estimator (XPE) downloadable at www.xilinx.com/products/technology/power/xpe.html... -
Page 13: Functional Description
SpaceWire SFVA784 DDR4 Thin Pipe 72 bit Thin Pipe SpaceWire 48 SE Level Translation 24 LVDS (Bypass Option) Level Translation Power Level 8 SE Translation TI SEP 8 MIO Figure 2 : ADM-VB630 Block Diagram Functional Description Page 7 ad-ug-1540_v1_0.pdf... -
Page 14: Switch Definitions
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.1.1 Switch Definitions There are two sets of eight DIP switches placed on the bottom of the board. Their functions are described below. Note: All switches are OFF by default. Factory Configuration switch must be in the OFF position for normal operation. -
Page 15: Led Definitions
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.1.2 LED Definitions There are seven LEDs on the rear of the board which can be used to provide a visual indication of the board status. Their locations are shown in Figure 3... -
Page 16: Table 7 Sysmon Leds
ADM-VB630 User Manual V1.0 - 7th Jan 2025 There are two LEDs available connected to MIO Bank501 which are intended to be used as system monitor LEDs, See Table 22 Adaptive SoC Comp. Ref. Bank Operation D1 (Red) PL Bank 501... -
Page 17: Vpx P0 Interface
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.2 VPX P0 Interface 4.2.1 SYSRESET# SYSRESET# is an active low input from the system controller SYSRESET# is connected to the Adaptive SoC PL side on Bank 302 (Pin F14)(LVCMOS33) SYSRESET# is connected to the Adaptive SoC PS side PCIe reset pins, LPD_MIO18 and LPD_MIO19 on Bank 502 (Pins W5 and Y6) 4.2.2 AUXCLK... -
Page 18: Single Ended Pl Gpio[55:48]
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.4.2 Single Ended PL GPIO[55:48] 1 Byte of Single Ended GPIO on P2 is routed to/from Adaptive SoC bank 702 and is compatible with 3.3V single ended signals at the VPX connector. -
Page 19: Jtag Interface
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.5 JTAG Interface 4.5.1 On-board Interface A JTAG boundary scan chain is connected to header J2. This allows the connection of the AMD JTAG cable via adapter board AD-JTAG-ADPT2. Adapter board AD-JTAG-ADPT2 should be inserted into header J2 through the rear of the board, header J2 is keyed to ensure correct orientation. -
Page 20: Clocks
These clocks can be combined with the Adaptive SoC's internal PLLs to suit a wide variety of communication protocols. A complete overview of the clock routing on the ADM-VB630 is given in Clocks. A description of each clock follows. -
Page 21: Ddr4 Memory Reference Clock (Mem_Clk)
There is a programable clock source that is forwarded throughout the Adaptive SoC. This clock is programmable through the Alpha Data ADK-VA601 SDK. PROGCLK is generated by a dedicated programmable clock generator IC that offers extremely high frequency resolutions (1ppm increments). -
Page 22: Adaptive Soc Ps Block
Note: all other possible switch settings are reserved / invalid. 4.8.2 Configuration Daughter Board The ADM-VB630 board has a socket (J1) that allows custom configuration boards to be used. The ADM-SDEV-FL1 configuration daughter board is supplied with the ADM-VB630 board as part of the ADK-VA601 development kit. -
Page 23: Can Interfaces
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.8.5 CAN interfaces Two CAN interfaces are routed to Rad hard transceiver chips on the board. Signal Bank Type Standard CAN0_TX LVCMOS33 CAN0_RX LVCMOS33 CAN1_TX LVCMOS33 CAN1_RX LVCMOS33 Table 15 : CAN PL side connections The other sides of the CAN transceivers are routed out to the VPX P2 connector. -
Page 24: Ddr4 Memory
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Name Function OE_L Output Enable : 0=ENABLED 1=DISABLED Direction Control : 0=INPUT 1=OUTPUT Table 19 : Buffer Pins 4.9.5 DDR4 Memory One bank of DDR4 SDRAM memory is soldered down to the board. The available density of the memory is 8GB. -
Page 25: System Monitor Status Leds
ADM-VB630 User Manual V1.0 - 7th Jan 2025 4.10.2 System Monitor Status LEDs If enabled for this function, LEDs D2 (Green) and D1 (Red) indicate the sysmon status. LEDs Status Flashing Green + Flashing Red (alternate) Service Mode Missing application firmware or invalid firmware... -
Page 26: Configuration
If you followed the previous steps, the Adaptive SoC should have been correctly configured. To verify this, power off the ADM-VB630, set switches SW2-1, SW2-3, SW2-4 ON and SW2-2 OFF. Then power up the ADM-VB630. Both the DONE_L and STAT_0 LEDs should illuminate after a few seconds(see Definitions) 4.11.2 Configuration From uSD Flash Memory... -
Page 27: Configuration Via Jtag
Copy the .pdi to FAT32 SD card and rename it to BOOT.bin The uSD card is now ready to be booted from. It can be inserted in the ADM-VB630 with the appropriate boot switch setting. The example design will be programmed into the Adaptive SoC automatically at boot. - Page 28 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Page Intentionally left blank Page 22 Functional Description ad-ug-1540_v1_0.pdf...
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Page 29: Appendix A: P1 Pin Assignments
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Appendix A: P1 Pin Assignments Appendix A.1: Data Plane 1 (P1 Wafers 1-4) Signal VPX P1 ACAP ACAP VPX P1 Signal P1_TX0_N P1_RX0_N P1_TX0_P P1_RX0_P P1_TX1_N P1_RX1_N P1_TX1_P P1_RX1_P P1_TX2_N P1_RX2_N P1_TX2_P... -
Page 30: Spacewire Interface (P1 Wafers 13-16)
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Signal (DIFF) VPX P1 ACAP ACAP VPX P1 Signal (DIFF) UART0_TXD UART0_RXD Table 26 : SpaceWire Interface (P1 Wafer 12) Appendix A.5: SpaceWire Interface (P1 Wafers 13-16) Signal (DIFF) VPX P1 ACAP (SE) -
Page 31: Appendix B: P2 Pin Assignments
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Appendix B: P2 Pin Assignments Appendix B.1: GPIO (P2 Wafers 1-14) Signal VPX P2 ACAP ACAP VPX P2 Signal GPIO<0> GPIO<28> GPIO<1> GPIO<29> GPIO<2> GPIO<30> GPIO<3> GPIO<31> GPIO<4> GPIO<32> GPIO<5> GPIO<33> GPIO<6>... -
Page 32: Mio (P2 Wafers 15-16)
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Signal VPX P2 ACAP ACAP VPX P2 Signal GPIO_DIR2_<0> GPIO_DIR2_<2> GPIO_DIR2_<1> GPIO_DIR2_<3> Table 28 : GPIO (P2 Wafers 1-14) Appendix B.2: MIO (P2 Wafers 15-16) Signal VPX P2 ACAP ACAP VPX P2 Signal MIO<16>... -
Page 33: Appendix C: Mio Map
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Appendix C: MIO Map Pin Number Pin Name Signal Name Comment PMC_MIO0_500 QSPI0_CLK Dual-Parallel Quad SPI PMC_MIO1_500 QSPI0_IO[1] Dual-Parallel Quad SPI PMC_MIO2_500 QSPI0_IO[2] Dual-Parallel Quad SPI PMC_MIO3_500 QSPI0_IO[3] Dual-Parallel Quad SPI PMC_MIO4_500... - Page 34 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Pin Number Pin Name Signal Name Comment PMC_MIO34_501 UNUSED UNUSED PMC_MIO35_501 UNUSED UNUSED PMC_MIO36_501 VPX_GA_IN0 VPX Signal PMC_MIO37_501 VPX_GA_IN1 VPX Signal PMC_MIO38_501 VPX_GA_IN2 VPX Signal PMC_MIO39_501 VPX_GA_IN3 VPX Signal PMC_MIO40_501 VPX_GA_IN4 VPX Signal...
- Page 35 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Pin Number Pin Name Signal Name Comment LPD_MIO18_502 PERST_PL_L Reset Input LPD_MIO19_502 PERST_PL_L Reset Input LPD_MIO20_502 VPX_PS_SCL VPX I2C SCL LPD_MIO21_502 VPX_PS_SDA VPX I2C SDA LPD_MIO22_502 I2C0_SCL I2C to Config socket LPD_MIO23_502...
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Page 36: Appendix D: Ddr4 Pinout Table
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Appendix D: DDR4 Pinout Table Pin Number Signal Name ACAP Bank AB12 DDR4_0_A<0> AE22 DDR4_0_A<1> AB17 DDR4_0_A<10> AE13 DDR4_0_A<11> AH12 DDR4_0_A<12> AD15 DDR4_0_A<13> AD21 DDR4_0_A<14> AD17 DDR4_0_A<15> AD22 DDR4_0_A<2> AB15 DDR4_0_A<3> AD12 DDR4_0_A<4>... - Page 37 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Pin Number Signal Name ACAP Bank DDR4_0_DM<7> DDR4_0_DM<8> AD25 DDR4_0_DQ<0> AF25 DDR4_0_DQ<1> AG28 DDR4_0_DQ<10> AE27 DDR4_0_DQ<11> AH27 DDR4_0_DQ<12> AD26 DDR4_0_DQ<13> AE26 DDR4_0_DQ<14> AF26 DDR4_0_DQ<15> AH18 DDR4_0_DQ<16> AH17 DDR4_0_DQ<17> AH22 DDR4_0_DQ<18> AH15 DDR4_0_DQ<19>...
- Page 38 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Pin Number Signal Name ACAP Bank AE24 DDR4_0_DQ<4> DDR4_0_DQ<40> DDR4_0_DQ<41> DDR4_0_DQ<42> DDR4_0_DQ<43> DDR4_0_DQ<44> AA22 DDR4_0_DQ<45> DDR4_0_DQ<46> AA21 DDR4_0_DQ<47> DDR4_0_DQ<48> DDR4_0_DQ<49> AG25 DDR4_0_DQ<5> DDR4_0_DQ<50> DDR4_0_DQ<51> DDR4_0_DQ<52> DDR4_0_DQ<53> DDR4_0_DQ<54> DDR4_0_DQ<55> DDR4_0_DQ<56> DDR4_0_DQ<57> DDR4_0_DQ<58> DDR4_0_DQ<59>...
- Page 39 ADM-VB630 User Manual V1.0 - 7th Jan 2025 Pin Number Signal Name ACAP Bank AG26 DDR4_0_DQ<8> AG27 DDR4_0_DQ<9> AF23 DDR4_0_DQS0_C AF24 DDR4_0_DQS0_T AD27 DDR4_0_DQS1_C AC28 DDR4_0_DQS1_T AH19 DDR4_0_DQS2_C AG20 DDR4_0_DQS2_T AG16 DDR4_0_DQS3_C AG17 DDR4_0_DQS3_T DDR4_0_DQS4_C DDR4_0_DQS4_T AA23 DDR4_0_DQS5_C DDR4_0_DQS5_T DDR4_0_DQS6_C...
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Page 40: Revision History
ADM-VB630 User Manual V1.0 - 7th Jan 2025 Revision History Date Revision Nature of Change Initial Draft 21 Oct 2024 Fixed error in PSU table 06 Nov 2024 Updated block diagram 15 Nov 2024 First release after review 07 Jan 2025...
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