Clocking; Pcie Reference Clocks; Fabric Clock; Table 5 Pcie Reference Clocks - Alpha Data ADM-PCIE-9V3 User Manual

3.2 Clocking

The ADM-PCIE-9V3 provides reference clocks for the DDR4 SDRAM banks and the I/O interfaces available to
the user. After a clock is programmed to a certain frequency, that frequency will become the default on power-up.
Any clock out of an Si5338 Clock Synthesizer is re-configurable from either the front panel USB
the Alpha Data bridge IP available in the board support package (sold separately). This allows the user to
configure almost any arbitrary clock frequencies during application run time. Maximum clock frequency is
312.5MHz.
Note: use "set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]" to ensure the user
design does not interfere with the I2C interface to the reprogramable clock generator.
Card Edge PCIe Ref Clock (100MHz)
25MHz
30ppm
Source
CAPI Cable Clock (156.25MHz when used)

3.2.1 PCIe Reference Clocks

The 16 MGT lanes connected to the PCIe card edge use MGT quads 224 through 227 and use the system 100
MHz clock (PCIE_REFCLK).
PCIE_REFCLK1
PCIE_REFCLK2

3.2.2 Fabric Clock

The design offers a fabric clock called FABRIC_CLK which is permanently fixed at 300 MHz. This clock is
intended to be used for IDELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC)
pin.
Page 8
NB6L11S
Fanout
NB6L11S
Fanout
Si5338
Clock NB6L11S
Synth Fanout
Figure 9 : Clock Topology
Signal Target FPGA Input
MGTREFCLK0_226
MGTREFCLK0_224
Table 5 : PCIe Reference Clocks
NB6L11S
PCIe Ref Clock (MGTREFCLK0_226)
Fanout
PCIe Ref Clock (MGTREFCLK0_224)
QSFP28 161.1328125MHz Factory Default (MGTREFCLK0_127)
QSFP28 161.1328125MHz Factory Default (MGTREFCLK0_128)
CAPI 161.1328125MHz Factory Default (MGTREFCLK0_124)
CAPI 161.1328125MHz Factory Default (MGTREFCLK0_125)
Memory Interface Clock 300Mhz (IO Bank 44)
Memory Interface Clock 300Mhz (IO Bank 64)
FABRIC_CLK 300MHz (IO Bank 64)
NB6L11S
CAPI Cable Clock (MGTREFCLK1_124)
Fanout
CAPI Cable Clock (MGTREFCLK1_125)
I/O Standard
HCSL
HCSL
ADM-PCIE-9V3 User Manual
USB Interface
"P" pin "N" pin
AA7 AA6
AJ7 AJ6
Functional Description
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