Qsfp28; Table 12 Qsfp28 Part Numbers; Figure 11 Qsfp Locations - Alpha Data ADM-PCIE-9V3 User Manual

3.5 QSFP28

Two QSFP28 cages are available at the front panel. Both cages are capable of housing either active optical or
passive copper QSFP28 or QSFP compatible components. The communication interface can run at up to
28Gbps per channel. There are eight channels between the two QSFP28 cages (total maximum bandwidth of
224Gbps). These cages are ideally suited for 8x 25G or 2x 100G Ethernet or any other protocol supported by the
Xilinx GTY Transceivers. Please see Xilinx User Guide UG578 for more details on the capabilities of the
transceivers.
Both QSFP28 cages have control signals connected to the FPGA. Their connectivity is detailed in the
Pinout Table at the end of this document. The notation used in the pin assignments is QSFP0 and QSFP1 with
locations clarified in the diagram below.
Use the QSFP*_SEL_1V8_L in conjunction with the OPTICAL_SCL_1V8 and OPTICAL_SDA_1V8 pins as
detailed in Complete Pinout Table
Note:
The LP_MODE (Low Power Mode) to each QSFP28 cage is tied to ground.
The order options for the ADM-PCIE-9V3 include an option to fit the QSFP28 optical transceivers. The table
below shows the part number for the transceivers fitted with each option.
Order Code
Q10
Q14
Q25
Page 12
to communicate with QSFP28 register space.
Figure 11 : QSFP Locations
Description
40G (4x10) QSFP Optical Transceiver
56G (4x14) QSFP Optical Transceiver
100G (4x25) QSFP28 Optical Transceiver
Table 12 : QSFP28 Part Numbers
ADM-PCIE-9V3 User Manual
Part Number
FTL410QE2C
FTL414QB2C
FTLC9551REPM
Functional Description
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