Pci Express; Ddr4 Sdram - Alpha Data ADM-PCIE-9V3 User Manual

ADM-PCIE-9V3 User Manual

3.3 PCI Express

The ADM-PCIE-9V3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes. The FPGA drives these lanes directly
using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is
generally automatic and does not require user intervention.
PCI Express reset (PERST#) connected to the FPGA at two locations. See
PERST_1V8_0 and PERST_1V8_1.
The other pin assignments for the high speed lanes are provided in the pinout attached to the
Table
The PCI Express specification requires that all add-in cards be ready for enumeration within 120ms after power
is valid (100ms after power is valid + 20ms after PERST is released). The ADM-PCIE-9V3 does meet this
requirement when configured from a tandem bitstream with the proper SPI constraints detailed in the section:
Configuration From Flash Memory. For more details on tandem configuration, see Xilinx xapp 1179.
Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG239 for more details).

3.4 DDR4 SDRAM

Two banks of DDR4 SDRAM memory are soldered down to the board. While the factory default is 8GB/per bank,
16GB/bank is also supported through a built variant. Please see
interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is 2400 MT/s for 16GB total and
2133MT/s with 32GB total.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) tool. An example memory
exerciser project is included in the ADM-PCIE-9V3 SDK. All constraint information is included in
Table. Alpha Data has also provided a custom csv timing file for use with Xilinx MIG. This can be downloaded
from the ADM-PCIE-9V3 product page.
8Gb components used (standard) are Samsung K4A8G085WB-BCRC
16Gb components used (build variant) are Micron MT40A2G8PM-093E
When using the timing files provided on the alpha data product page
samsung timing files, as they are more relaxed than the micron variants.
Functional Description
ad-ug-1322_v2_7.pdf
Complete Pinout Table
Order Code for all order options. The memory
custom_parts_2400.csv
signals
Complete Pinout
Complete Pinout

, always use the
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