Functional Description; Overview; Figure 5 Adm-Pcie-9V3 Block Diagram - Alpha Data ADM-PCIE-9V3 User Manual

ADM-PCIE-9V3 User Manual

3 Functional Description

3.1 Overview

The ADM-PCIE-9V3 is a versatile reconfigurable computing platform with a Virtex UltraScale VU3P FPGA, a
Gen3x16 PCIe interface, two banks of DDR4 both 72 bits wide (for 64 bits with 8 bits ECC), two QSFP28 cages
capable of 8x 28G or 2x 112G Serial IO of any Xilinx supported standard (Ethernet, SRIO, Infiniband, etc.), one
OpenCAPI compatible Ultraport SlimSAS connector also capable of 28G/channel, an input for a timing
synchronization input, a 12 pin header for general purpose use (clocking, control pins, debug, etc.), and a robust
system monitor.
USB
QSFP28 Cage
(4x28 Gbps max)
QSFP28 Cage
(4x28 Gbps max)
Functional Description
ad-ug-1322_v2_7.pdf
Auxiliary IO
x8 SPI
(gpio, timing)
Config
System
Monitor
HRIO HRIO
JTAG
0
XCVU3P-2
MGT
FFVC1517I
MGT
MGT MGT
(0,4) (5,7)
x16 PCIe Gen3/4 Edge
Figure 5 : ADM-PCIE-9V3 Block Diagram
OpenCAPI SAS
(8x28Gbps max)
MGT MGT
x72
HPIO
x72
HPIO
MGT MGT
MAC ID
EEPROM
(8,11) (12,15)
DDR4 Bank 0
DDR4-2400/1866, 8/16GB
DDR4 Bank 1
DDR4-2400/1866, 8/16GB
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