Appendix: SmartDesign Implementation
The following table shows SmartDesign blocks in Adaptive FIR filter.
Table 4 •
Adaptive FIR Filter Demo Smart Design Blocks and Description
S.No Block Name
1
Adaptive_FIR
2
DATAHANDLE_FSM
3
FILTERCONTROL_FSM
4
LMS_FIR_TOP
5
INPUT_Buffer
OUTPUT_Buffer
FFT_Im_Buffer
FFT_Re_Buffer
6
COREFFT
The following table shows SmartDesign blocks in LMS_FIR_TOP.
Table 5 •
LMS_FIR_TOP Smart Design Blocks and Description
S.No Block Name
1
LMS_ALGO
2
LMS_CONTROL_FSM FSM implemented in RTL to control LMS_ALGO block
3
COREFIR
Description
FIR_FILTER_0 is a System Builder generated component, in which MMUART is
configured to handle the communication between the host PC and fabric logic. To
generate a System Builder component, refer to the
User
Guide.
Control logic to send/receive the data between MSS and data buffers
Control logic to generate the control signals for FIR and FFT operations
SmartDesign
FIR input signal data buffer
FIR output signal buffer
FFT output imaginary data buffer
FFT output real data buffer
COREFFT IP
Description
LMS algorithm implemented in RTL to compute error, correction factor, and filter
coefficients.
COREFIR IP
DG0441 Demo Guide Revision 7.0
SmartFusion2 System Builder
26
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