Microsemi SmartFusion2 Demo Manual
  1. Manuals
  2. Brands
  3. Microsemi Manuals
  4. Motherboard
  5. SmartFusion2 MSS
  6. Demo manual

Microsemi SmartFusion2 Demo Manual

Soc fpga in-system programming using uart interface - libero soc v11.8
Hide thumbs Also See for SmartFusion2:
Table of Contents

Advertisement

Quick Links

Download this manual See also: Configuration Manual, Demo Manual
DG0454
Demo Guide
SmartFusion2 SoC FPGA In-System Programming
Using UART Interface - Libero SoC v11.8

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SmartFusion2 and is the answer not in the manual?

Questions and answers

Related Manuals for Microsemi SmartFusion2

Summary of Contents for Microsemi SmartFusion2

  • Page 1 DG0454 Demo Guide SmartFusion2 SoC FPGA In-System Programming Using UART Interface - Libero SoC v11.8...
  • Page 2 Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this...

  • Page 3: Table Of Contents

    Contents 1 Revision History ........... . . 1 Revision 8.0 .
  • Page 4 Figure 16 SmartFusion2 Security Evaluation Kit Silkscreen Top View ......16 Figure 17 Configuring Export Bitstream .
  • Page 5 SmartFusion2 Security Evaluation Kit Jumper Settings ........

  • Page 6: Revision History

    Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 8.0 Updated the document for Libero v11.8 software release. Revision 7.0 Updated the design files for Libero v11.6 software release (SAR 72612).

  • Page 7: In-System Programming Using Uart Interface

    • FPGA fabric • Both the eNVM and the FPGA fabric For information on different programming modes supported by SmartFusion2 SoC FPGAs, see the UG0451: IGLOO2 and SmartFusion2 Programming User Guide. For information on system controller programming services, see the UG0450: SmartFusion2 SoC and IGLOO2 FPGA System Controller User Guide.

  • Page 8: Features

    The following figure describes the top-level demo. The SmartFusion2 device application configures the MMUART_1 peripheral for serial communication and initializes the system controller to run the ISP service. The UART Host PC Loader initiates the communication with the SmartFusion2 device through ®...

  • Page 9: Description

    2.2.2 Description The ISP in SmartFusion2 devices is performed by the Cortex-M3 processor and the system controller. The system controller manages the SmartFusion2 device programming and handles the system service requests. The SmartFusion2 device allows the Cortex-M3 processor to directly provide a bitstream to the system controller for programming.

  • Page 10: Table 2 Isp Operation Modes

    SmartFusion2 device. The SmartFusion2 device initializes the system controller and starts the ISP service in the chosen operation mode. On receiving the data request from the SmartFusion2 device, the UART Host PC Loader transfers the input source programming file in blocks of 4 Kb data with cyclic redundancy check (CRC). The SmartFusion2 device: •...

  • Page 11: Setting Up The Demo Design

    Setting Up the Demo Design The following steps describe how to set up the demo design: Connect the FlashPro4 programmer to the J5 connector of the SmartFusion2 Security Evaluation Kit board. Connect the host PC to the J18 connector using the USB Mini-B cable. The USB to UART bridge drivers are automatically detected.

  • Page 12: Figure 4 Device Manager Window

    Figure 4 • Device Manager Window Connect the jumpers on the SmartFusion2 Security Evaluation Kit board as listed in the following table. Caution: Switch off the SW7 switch on the board while making the jumper connections. Table 3 •...

  • Page 13: Running The Demo Design

    In-System Programming Using UART Interface Running the Demo Design Download the demo design from: http://soc.microsemi.com/download/rsc/?f=m2s_dg0454_liberov11p8_df Switch ON the SW7 power supply switch. Launch the FlashPro software. Click New Project. In the New Project window, type the project name. Figure 5 •...

  • Page 14: Figure 6 Flashpro Project Configured

    ISP service. So, the SmartFusion2 device is preprogrammed with the isp_demo.stp using FlashPro software. LEDs 4 to 7 (H5, H6, J6, H7) blinking in the board indicates that the SmartFusion2 Device fabric is preprogrammed successfully. Figure 7 •...

  • Page 15: Example Command

    2.4.2 Resetting the board If the UART Host PC Loader is not connected to the SmartFusion2 Security Evaluation Kit board, press the switch, SW6 to reset the board. The following figure shows an example message that instructs to reset the board.

  • Page 16: Verify Operation Mode

    Figure 11 • ISP Verification Status The verification operation demonstrated is for the isp_demo.stp file that is already running in the SmartFusion2 device. If any other .spi file is verified while the isp_demo.stp file is still running, that verification operation fails.

  • Page 17: Program Operation Mode

    In-System Programming Using UART Interface Press SW6 to reset the SmartFusion2 Security Evaluation Kit to try other ISP operation modes from CMD prompt window. Figure 12 • ISP Verification Failure Error Message Program Operation Mode To program the FPGA fabric and the eNVM of the SmartFusion2 device using the isp_fabric_and_envm.spi file, type:...

  • Page 18: Checking If The Envm Is Programmed Successfully

    FPGA fabric Programming Result isp_envm_only.spi The serial terminal emulation program shows successful eNVM program message isp_fabric_only.spi SmartFusion2 LEDs 0 to 3 blinks isp_fabric_and_envm.spi The serial terminal emulation program SmartFusion2 LEDs 0 to 3 blinks shows successful eNVM program message Note: After successful ISP Program operation, the Security Evaluation Kit must be reprogrammed with the original isp_demo.stp file to try the ISP operation modes again.

  • Page 19: Known Issue

    Errata. The workaround for this problem is to put the device in Flash *Freeze and exit from Flash *Freeze after the IAP or ISP program operation. Microsemi recommends that this workaround is implemented for any design, which accesses LSRAM after IAP or ISP. For more information about how to implement this...

  • Page 20: Appendix: Board Setup For Running The Demo

    Appendix: Board Setup for Running the Demo Appendix: Board Setup for Running the Demo The following figure shows the board setup for running the demo on the SmartFusion2 Security Evaluation Kit board. Figure 15 • Board Setup for Running the Demo...

  • Page 21: Appendix: Jumper Locations

    Appendix: Jumper Locations Appendix: Jumper Locations The following figure shows the jumper locations in SmartFusion2 Security Evaluation Kit board. Figure 16 • SmartFusion2 Security Evaluation Kit Silkscreen Top View SF2-GPIO D7 D6 D4 D3 FTDI-GPIO 12V I/P PROG Header LED2...

  • Page 22: Appendix: Error Codes

    Appendix: Error Codes Appendix: Error Codes The following table lists the error codes in SmartFusion2 Security Evaluation Kit board. Table 5 • Error Codes Error Define Code Description #define MSS_SYS_CHAINING_MISMATCH Device contents mismatch #define MSS_SYS_UNEXPECTED_DATA_RECEIVED Data is not supported #define MSS_SYS_INVALID_ENCRYPTION_KEY...

  • Page 23: Appendix: Generating .Spi Programming File Using Libero

    Appendix: Generating .spi Programming File using Libero Appendix: Generating .spi Programming File using Libero The following steps describe how to generate .spi programming file using the Libero SoC software: Launch the Libero SoC software to open a Libero project for isp_fabric_and_envm.spi programming file.

  • Page 24: Figure 18 Export Programming File Options Window

    Appendix: Generating .spi Programming File using Libero On the Export Bitstream window, select the SPI file check box. Figure 18 • Export Programming File Options Window 4. Click OK. 5. Double-click Export Bitstream under Handoff Design for Production in the Design Flow tab to generate the .spi file (Figure 17, page 18).

  • Page 25: Appendix: Hardware Project Implementation Settings

    Appendix: Hardware Project Implementation Settings Appendix: Hardware Project Implementation Settings The following hardware project settings are required to build the demo design. Configuring the I/Os for Flash*Freeze Mode The Libero demo design configures M3_CLK to operate at 50MHz and one UART interface (MMUART_1) for serial communication.

  • Page 26: Softconsole Project Generation

    Appendix: Hardware Project Implementation Settings SoftConsole Project Generation The firmware can be generated by checking the Create Project and selecting a Software IDE option in Libero project as shown in the following figure. Figure 22 • Export Firmware Options On successful firmware generation, the firmware and SoftConsole folders are generated at <download_folder>\sf2_isp_using_uart_interface_demo_df\libero as specified in Location field of Export Firmware dialog box, as shown in the following figure.
  • Page 27 Appendix: Hardware Project Implementation Settings • demo_MSS_CM3_boot_loader This project implements the remapping of the eSRAM to Cortex-M3 processor code space after copying the ISP code to eSARM from eNVM. • demo_MSS_CM3_hw_platform This project contains all the firmware and hardware abstraction layers that correspond to the hardware design.

  • Page 28: Appendix: Implementing Workaround To Access Fabric Lsram After Iap/Isp Program

    Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation The LSRAM write and read accesses are denied after implementing IAP or ISP program operation. The workaround for this problem is to apply System Reset after IAP or ISP program operation. This workaround can be implemented by one of the following ways.

  • Page 29: Figure 25 Tamper Macro Configuration Window

    Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation b. Select the Enable RESET Function check box in the Configuring Tamper 2_0 window. c. Click OK. The System Reset is enabled. Figure 25 • Tamper Macro Configuration Window The following figure shows the TAMPER2_0 macro after configuration.

  • Page 30: Figure 27 Ram_Interafce Fsm Component

    Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation Instantiate the FSM Module provided in the design files. This FSM Logic performs 3 consecutive address writes to the Two-Port Large SRAM with the known data pattern and then reads back data from those 3 consecutive address locations to compare.

  • Page 31: Figure 28 Two-Port Sram Configurator Window

    Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation Drag-and-drop the Two-Port Large SRAM (TPSRAM) available in the Libero Catalog to the Dev_Restart_after_ISP_blk SmartDesign canvas. Configure the TPSRAM with the following settings: – Write Port • Depth: 64 •...

  • Page 32: Figure 29 Dev_Restart_After_Isp_Blk Smartdesign

    Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation Make the connections for Tamper Macro, FSM, and TPSRAM, as shown in the following figure. Figure 29 • Dev_Restart_after_ISP_blk SmartDesign Click the demo_top tab and drag-and-drop the Dev_Restart_after_ISP_blk component from the Design Hierarchy to the demo_top SmartDesign canvas.

  • Page 33: Importing The .Cxf File

    Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program Operation Importing the .cxf File Import the .cxf file for SmartDesign Dev_Restart_after_ISP_blk. This .cxf file is provided with the design files and it has all the component instantiations and connections mentioned in Using SmartDesign, page 23 from step 1 to 6.

Table of Contents