Figure 29 Dev_Restart_After_Isp_Blk Smartdesign; Figure 30 Demo_Top Smartdesign - Microsemi SmartFusion2 Demo Manual

Soc fpga in-system programming using uart interface - libero soc v11.8

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Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program

Operation

Make the connections for Tamper Macro, FSM, and TPSRAM, as shown in the following figure.

Figure 29 • Dev_Restart_after_ISP_blk SmartDesign

Click the demo_top tab and drag-and-drop the Dev_Restart_after_ISP_blk component from the

Design Hierarchy to the demo_top SmartDesign canvas.

Make the connection as shown in the following figure and generate demo_top SmartDesign. This

completes the implementation of the workaround.

Figure 30 • demo_top SmartDesign

Note: This workaround is applicable for v11.5 software release or later, and must be implemented in the Libero

design, which is used to generate the .spi programming file. Older versions of Libero might prune

Tamper Macro during Synthesis. To avoid pruning, one of the recommended options is to promote the

DETECT_ATTEMPT signal of Tamper Macro to the top-level.

DG0454 Demo Guide Revision 8.0

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