Appendix: Hardware Project Implementation Settings; Configuring The I/Os For Flash*Freeze Mode; Standby Clock Source Configuration; Figure 20 Configuring Mmuart_1 Ports To Be Available During F*F - Microsemi SmartFusion2 Demo Manual

Appendix: Hardware Project Implementation Settings

7 Appendix: Hardware Project Implementation
Settings
The following hardware project settings are required to build the demo design.
7.1

Configuring the I/Os for Flash*Freeze Mode

The Libero demo design configures M3_CLK to operate at 50MHz and one UART interface
(MMUART_1) for serial communication. The FPGA fabric is not operational during Program or Verify
operations as the device enters into Flash*Freeze (F*F). On the Security Evaluation Kit board, the
MMUART_0 TX and RX are connected to the mini-B USB through the fabric and fabric I/Os. During F*F
mode, the fabric and I/Os are not available. So the MMUART_0 cannot be used as the serial
communication interface. As such, MMUART_1 is used, and the RXD and TXD ports are configured
using the I/O Editor to be available during F*F mode, as shown in the following figure. The user has to
Check the settings from the File menu after configuring the ports.
Figure 20 • Configuring MMUART_1 Ports to be Available During F*F
7.2

Standby Clock Source Configuration

The standby clock source for the MSS in F*F mode is configured to On-chip 50 MHz RC Oscillator using
the Flash*Freeze Hardware Settings dialog in the Libero SoC software, as shown in the following figure.
A higher MSS clock frequency is required in F*F mode to meet the MMUART baud rate requirements.
Figure 21 • Flash*Freeze Hardware Settings Dialog Box
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