Figure 27 Ram_Interafce Fsm Component - Microsemi SmartFusion2 Demo Manual

Appendix: Implementing Workaround to Access Fabric LSRAM after IAP/ISP Program
Operation
4. Instantiate the FSM Module provided in the design files. This FSM Logic performs 3 consecutive
address writes to the Two-Port Large SRAM with the known data pattern and then reads back data
from those 3 consecutive address locations to compare. If the read back data pattern does NOT
match with the written data pattern, then the FSM asserts the RESET_N input to Tamper Macro,
which in turn causes a System Reset. If the read back data pattern matches with the written data
pattern, then the FSM does not do anything. Follow the steps to add the FSM logic to the PCIe IAP
design:
a. Choose File > Import > HDL Source Files.
b. Browse to the following Ram_interface.v file location in the design files folder.
<download_folder>\sf2_isp_using_uart_interface_demo_df\Source_files
c. Click the Dev_Restart_after_ISP_blk tab and drag-and-drop the Ram_interface component
from the Design Hierarchy to the Dev_Restart_after_ISP_blk SmartDesign canvas. The following
figure shows the Ram_interface component.
Figure 27 • Ram_interafce FSM Component
Upon completion of IAP programming, the System Controller asserts POWER_ON_RESET_n to
FPGA fabric. This triggers the RESETn signal and initiates the state machine in the FSM module.
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