Appendix: Jumper Locations; Figure 16 Smartfusion2 Security Evaluation Kit Silkscreen Top View - Microsemi SmartFusion2 Demo Manual

Soc fpga in-system programming using uart interface - libero soc v11.8
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Appendix: Jumper Locations

4
Appendix: Jumper Locations
The following figure shows the jumper locations in SmartFusion2 Security Evaluation Kit board.
Figure 16 • SmartFusion2 Security Evaluation Kit Silkscreen Top View
1
C7
C10
3
RMT
U4
SWT
12V I/P
J6
2
1
2
D9
SW7
4
3
ON
ETH PHY-SGMII
20
J13
17
J18
U11
1
CR2
GND
5
TP6
FTDI
TP8
1
CR3
U19
U20
TP9
4
5
J24
1
U25
3
USB
SW1
U26
Note: Jumpers highlighted in red are set by default.
Note: The location of the jumpers in Figure 16 are searchable.
G
60
G
G
50
G
TC2
TC1
GND
U2
D7 D6
TC5
TP2
U6
TC4
U8
1
L1
3
TP4
GND
L3
J7
LED2
TC7
TC8
1
L3
U9
J11
100MBPS LINK
J12
LPDDR
U10
U1
1
A1
1
DPR1
A
Y2
J14
Y1
U14
SERDES_REFCLK1P
Y3
CUR_VDDA_PLL
J17
U18
1
Active
CLK_EN
HZ
J23
CUR_PLL_L01
1
OSC
2P5V_LDO
J21
2
SERDES_REFCLK1
U22
SMA
1
C103
L20
J25 J26
L0
CON1
B1
B11 B12
B18
DG0454 Demo Guide Revision 8.0
G
40
G
30
G
G
20
G
G
10
20
15
10
5
D5
D4 D3
D2
C7
C6
C5
C4
C3
C2
B7
B6
B5
A7
A6
A5
A4
TP3
2
U7
J5
1
L19
L
PROG Header
1
RMT
2
JTAG_SEL
3
H
4
K20
J8
M2GL_M2S-EVAL-KIT
SW5
DVP-102-000402-001
4
2
Rev D
1
3
SW4
L5
U16
1 A
Y5
Y4
C79
XTAL
1P2V_CUR_SENSE
TP16
CUR_PLL_L23
1P2V
2P5V_LDO
TP10
TP17
U21
L6
GND
1
J27
1
A
U23
L7
U24 J28
TP14
SF2-GPIO
J1
G
J2
GND
FTDI-GPIO
TP1
20
10
2
J4
9
1
19
J9
20
B1
A1
2
DEVRST
SW6
A
B
1
19
I2C1_SDA
H1
U5
1
4
4
2
SW2
I2C0_SCL
1
3
13
16
L2
I2C0_SDA
TP5
GND
U15
SPI
TP18
TP19
1P8V
1P8V_CUR_SENSE
TP11
GND
SW3
TP7
GND 4
2
TP15
J30
PROBE A
3
1
GND
PROBE B
J29
16

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