Figure 1 Demo Design Files Top-Level Structure; Figure 2 Top-Level Demo Block Diagram - Microsemi SmartFusion2 Demo Manual

In-Application Programming Using PCIe Interface
The following figure shows the top-level structure of the design files. For more information, see the
Readme.txt file.
Figure 1 • Demo Design Files Top-Level Structure
The following figure describes the demo design. The arrows in red show the data flow between the host
PC and the on-board external serial peripheral interface (SPI) flash memory using the PCIe interface.
®
The ARM Cortex
using the large static random access memory (LSRAM) memory as a temporary buffer.
The lines in blue show the system controller reading data from the external SPI flash memory to program
the SmartFusion2 device. For more information about IAP process, see
Figure 2 • Top-Level Demo Block Diagram
PCIe Interface
GUI
Host PC
Step1
Transferring data bitstream from host PC to external Flash through PCIe interface
Step2
System controller reads data bitstream from the external flash to program the SmartFusion2 device
<download_folder>
sf2_iap_using_interface_demo_df
®
-M3 processor copies the programming data from the host PC to the SPI flash by
System Controller
eNVM
Cortex – M3
COMM_BLK
FIC_0
S
M
CoreAHBLite
M
S
CoreAHB
LSRAM
Serial Controller 0
(PCIe(x4) GEN 2)
DG0584 Demo Guide Revision 5.0
libero
pcie_driver
sample_programming_files
staple_programming_file
readme.txt
Description,
APB_1 GPIO
APB_0
AHB Bus Matrix
SmartFusion2
page 4.
LEDs
Switches
External
SPI_0
SPI Flash
MSS
FPGA Fabric
3