Standby Clock Source Configuration; Figure 34 Flash*Freeze Hardware Settings - Microsemi SmartFusion2 Demo Manual

Soc fpga in-application programming using pcie interface - libero soc v11.8

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Appendix: Hardware Implementation

6.1

Standby Clock Source Configuration

The standby clock source for the MSS in the F*F mode is configured to On-chip 50 MHz RC Oscillator

using the Flash*Freeze Hardware Settings dialog box in the Libero SoC software, as shown in the

following figure. A higher MSS clock frequency is required in the F*F mode to meet the SPI

communication speed requirements.

Figure 34 • Flash*Freeze Hardware Settings

DG0584 Demo Guide Revision 5.0

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