Configuring I/Os For FlashFreeze Mode; Softconsole Project Generation; Figure 35 Configuring Spi_0 Ports Available During FF; Figure 36 Export Firmware Options - Microsemi SmartFusion2 Demo Manual

Soc fpga in-application programming using pcie interface - libero soc v11.8

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Appendix: Hardware Implementation

6.2

Configuring I/Os for Flash*Freeze Mode

The FPGA fabric is not operational during the Program or Verify IAP operations as the device enters into

the Flash*Freeze (F*F) mode. On the SmartFusion2 Security Evaluation Kit board, the SPI_0 is

interfaced to the on-board SPI Flash memory for loading the programming bitstream data to the SPI

Flash using the SPI interface. During the F*F mode, the fabric and I/Os are not available. Therefore, all

the SPI_0 ports are configured using the I/O Editor to be available during the F*F mode, as shown in the

following figure. Commit and Check the settings from the File menu after configuring the SPI_0 ports.

Figure 35 • Configuring SPI_0 Ports Available During F*F

6.3

The firmware and SoftConsole project workspace can be generated by selecting the Create project for

selected Software Tool Chain check box and selecting a Software ToolChain option from the drop-

down list, as shown in the following figure.

Figure 36 • Export Firmware Options

After successful firmware generation, the firmware and SoftConsole folders are generated at

<download_folder>\sf2_iap_using_interface_demo_df\libero as specified in the Location field of Export

Firmware dialog box shown in the above figure.

DG0584 Demo Guide Revision 5.0

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