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LPC Connector
SD330-Q170/H110
CPU Fan
2
6
2
6
PS/2 KB/MS
1
System Fan 1
1
USB 6
1
5
1
5
USB 5
2
6
2
6
USB 2.0
1
5
1
5
4
1
8
5
COM 1
+12V
VGA
Socket LGA1151
Power
Chrontel
CH7517A
ASMedia
ASM1442
DVI-D
DP++
Intel
LAN 1
WGI219LM
USB 2
USB 1
USB 3.0
LAN 2
USB 4
USB 3
Intel
USB 3.0
WGI210AT
Line-out
Battery
Mic-in
PCIe x16
PCI 1
Realtek
ALC888
1
S/PDIF
PCI 2
Buzzer
2
6
1
5
PCIe x4
ITE
1
IT8893E
NXP
USB 3.0
PTN3460
USB 2.0
(only for Q170)
1
Digital I/O
USB 5-6
1
39
USB 9-10
USB 7-8
9
1
9
1
11
20
19
1
10+
1
2
2
40
LVDS LCD Panel
10
2
10
LCD/Inverter Power
SD331-C236/Q170
I C
2
6
2
6
1
PS/2 KB/MS
CPU Fan
USB 6
1
5
1
5
USB 5
2
6
2
6
USB 2.0
1
5
1
5
4
1
8
5
COM 1
+12V
VGA
Socket LGA1151
Power
Chrontel
CH7517A
ASMedia
ASM1442
DVI-D
DP++
LAN 1
USB 2
Intel
USB 1
WGI219LM
USB 3.0
LAN 2
USB 4
USB 3
USB 3.0
Intel
WGI210AT
Battery
Line-out
Mic-in
PCIe 1 (PCIe x16 or PCIe x8)
Realtek
PCIe 2 (PCIe x4)
ALC888
S/PDIF
1
PCIe 3 (PCIe x8)
6
5
6
5
6
5
6
5
Nuvoton
PCIe 4 (PCIe x4)
1
NCT6106D
2
1
2
1
2
1
2
1
Chassis
Intrusion
USB 2.0
USB 5-6
USB 7-8
USB 9-10
USB 7-8
COM 2
COM 3
COM 4
9
1
9
1
9
1
9
1
9
1
11
11
10
1
10
1
10
2
10
2
10
2
10
2
10
2
Chapter 5 Ports and Connectors
TPM
14
13
(optional)
2 1
LPC
12
24
ATX
Power
Standby
Power LED
1
13
1
1
2
Front
Panel
11
12
1
2
LAN LED
7
8
SPI Flash
1
2
SPI
1
DDR4_1
DDR4_3
BIOS
Program
14 13
DDR4_2
Header
7
8
Chassis
DDR4_2
(only for Q170)
Intrusion
(only for Q170)
Mini PCIe
1
(only for Q170)
1
1
Intel
SATA 0
1
Q170
SATA 1
1
SATA 2
1
5
1
SMBus
6
5
SATA 3
2
1
6
2
2
6
2
6
2
6
SATA 3.0
1
5
1
5
1
5
2 1
1
1
9
1
9
1
9
1
9
1
9
1
System
Fan 2
2
10
2
10
2
10
2
10
2
10
2
COM 2
COM 3
COM 4
COM 5
COM 6
1
System Fan 2
14
13
TPM
(optional)
2 1
LPC
12
24
Standby
Power LED
ATX
Power
1
13
1
1
2
Front
Panel
11
12
1
2
LAN LED
1
DDR4_1
DDR4_3
7
8
DDR4_2
DDR4_4
SATA 3.0
1
1
SATA 0
SATA 1
Intel
1
1
Q170
SATA 2
SATA 3
SATA 4
SATA 5
1
1
5
1
System Fan 1
1
SMBus
6
2
SPI Flash
BIOS
Buzzer
9
1
9
1
1
19
DIO
2
10
2
10
2
COM 5
COM 6
Chapter 5
The Low Pin Count Interface was defined by Intel
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embedded
controllers. Data transfer on the LPC bus is implemented over a 4 bit serialized data interface,
which uses a 24MHz LPC bus clock. For more information about LPC bus, please refer to the
Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the pin as-
®
signments of the LPC connector.
Pin
Pin Assignment
1
L_CLK
3
L_RST#
5
L_FRAME#
7
L_AD3
9
L_AD2
11
INT_SERIRQ
13
5VSB
40
14 13
2 1
Corporation to facilitate the industry's transi-
®
Pin
Pin Assignment
2
L_AD1
4
L_AD0
6
3V3
8
GND
10
Kev
12
GND
14
5V
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