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Lattice Semiconductor
Signal Descriptions
Table 2-3. 10 Gb+ Ethernet MAC IP Core Input and Output Signals
Port Name
Active State
reset_n
tx_paustim[15:0]
tx_pausreq
Positive Edge
tx_is_paused
tx_data_avail
tx_read
tx_data[63:0]
tx_byten[2:0]
tx_eof
tx_force_err
tx_empty
tx_statvec[25:0]
tx_staten
rx_statvec[27:0]
rx_staten
ignore_pkt
rx_write
rx_data[63:0]
rx_byten[2:0]
rx_sof
IPUG39_02.9, December 2010
I/O Type
Low
Input
Asynchronous reset signal – Resets the entire core when asserted.
Contains parameters to be transmitted in a pause frame. Valid when
N/A
Input
tx_pausreq is asserted.
Input
Asserted to initiate the transmitting of a pause frame.
Active when the transmitter has been placed in the pause state by a
High
Output
received pause frame.
Asserted to alert the MAC transmitter that the transmit FIFO has data ready
High
Input
for transmission.
Transmit FIFO read request, asserted by the MAC transmitter in response
High
Output
to signal tx_data_avail.
Data read from transmit FIFO. The least significant byte (bits 7:0) is sent
N/A
Input
out on the link first.
Indicates the valid bytes on the tx_data bus. Must be 7 except when tx_eof
is active.
0 - tx_data[7:0] valid
1 - tx_data[15:0] valid
2 - tx_data[23:0] valid
N/A
Input
3 - tx_data[31:0] valid
4 - tx_data[39:0] valid
5 - tx_data[47:0] valid
6 - tx_data[55:0] valid
7 - tx_data[63:0] valid
High
Input
End of frame signal asserted with the last segment of the frame.
Indicates that the current frame has errors. This input is qualified with input
High
Input
signal tx_eof.
High
Input
When asserted, indicates that the transmit FIFO is empty.
Contains information on the frame transmitted (details given in the Func-
N/A
Output
tional Description section of this document). This bus is qualified by the
tx_staten signal.
When asserted, indicates that the contents of the tx_statvec bus are valid.
High
Output
This signal is asserted for 3 txmac_clk periods.
Contains information on the frame received (details given in the Functional
N/A
Output
Description section of this document). This bus is qualified by the rx_staten
signal.
When asserted, indicates that the contents of the rx_statvec bus are valid.
High
Output
This signal is asserted for 3 rxmac_clk periods.
Asserted to prevent a receive FIFO full condition. The Receive MAC will
High
Input
continue dropping packets as long as this signal is asserted.
High
Output
Driven by the MAC core to request a receive FIFO write.
N/A
Output
Contains data that is to be written into the receive FIFO.
Indicates the valid bytes on the rx_data bus. Must be 7 except when rx_eof
is active.
0 - rx_data[7:0] valid
1 - rx_data[15:0] valid
2 - rx_data[23:0] valid
N/A
Output
3 - rx_data[31:0] valid
4 - rx_data[39:0] valid
5 - rx_data[47:0] valid
6 - rx_data[55:0] valid
7 - rx_data[63:0] valid
High
Output
Start of frame signal asserted with the first segment of the frame.
Description
11
10 Gb+ Ethernet MAC IP Core User's Guide
Functional Description
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