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Lattice Semiconductor
Specifically:
• LatticeECP2: LFE235E-7F672C
• LatticeECP2S: LFE235ES-7F672C
• LatticeECP2M: LFE2M35E-7F672C
• LatticeECP2MS: LFE2M35SE-7F672C
• LatticeECP3: LFECP370E-8F1156CES
• LatticeECP3: LFECP3-35E-8F1156CES
• LatticeECP3: LFE3-150EA –8F 672CTW
• LatticeSC: LFSC3GA25E-5F900C
• LatticeSCM: LFSCM3GA25EP1-5F900C
Push-button implementation of both top-level configurations is supported via the Diamond or ispLEVER project
files, <username>_reference_eval.syn and <username>_core_only_eval.syn. These files are located in
\<project_dir>\ten_gbemac_test\ten_gbemac_eval\<username>\impl\<configuration>.
For the Linux platform, the top-level synthesis must be run separately with a synthesis tool such as Synplify Pro,
since Diamond or ispLEVER for Linux only accepts an EDIF entry. For the core only project, synthesis tcl files will
be generated for this purpose, including <username>_core_only_top.tcl in the directory
\<project_dir\ten_gbemac_eval\<username>\impl\core_only\synplify. The user can run this tcl
script to synthesize the core_only top_level files in the above directory.
For the reference project, <username>_reference_top.tcl will be generated in the
\<project_dir>\ten_gbemac_eval\<username>\impl\reference\synplify directory. The user can
run this tcl script to synthesize the reference top_level files in the above directory.
To use this project file in Diamond:
1. Choose File > Open > Project.
2. Browse to \<project_dir>\ten_gbemac_eval\<username>\impl\synplify (or precision) in
the Open Project dialog box.
3. Select and open <username>.ldf. At this point, all of the files needed to support top-level synthesis and imple-
mentation will be imported to the project.
4. Select the Process tab in the left-hand GUI window.
5. Implement the complete design via the standard Diamond GUI flow.
To use this project file in ispLEVER:
1. Choose File > Open Project.
2. Browse to \<project_dir>\ten_gbemac_eval\<username>\impl\synplify (or precision) in
the Open Project dialog box.
3. Select and open <username>.syn. At this point, all of the files needed to support top-level synthesis and imple-
mentation will be imported to the project.
4. Select the device top-level entry in the left-hand GUI window.
IPUG39_02.9, December 2010
22
10 Gb+ Ethernet MAC IP Core User's Guide
IP Core Generation
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