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Lattice Semiconductor
Pause Opcode (PAUS_OP_[0-1])
This register contains the PAUSE Opcode. This will be compared against the Opcode in the received PAUSE
frame. This value will also be included in any PAUSE frame transmitted by the MAC.
Table 5-12. Pause Opcode Register Description
Name: PAUS_OP_[0-1]
Bits
Name
7:0
Pause_OpCode_0
7:0
Pause_OpCode_1
Test Control Register (TSTCNTL)
Test control bits.
Table 5-13. Test Control Register Description
Name: TSTCNTL
Bits
Name
7:2
UNUSED
1
Loop back Enable
0
Address Swap
MAC Control Register (MACCNTL)
MAC control bits.
Table 5-14. MAC Control Register Description
Name: MACCNTL
Bits
Name
7:5
UNUSED
4
Ignore packet
3
Tx fifo empty
2
UNUSED
1
UNUSED
Tx Send Pause
0
Request
PAUSE Time Register (PAUSTMR)
This register has the pause time for a flow control packet sourced by the 10G+ MAC transmitter.
Table 5-15. PAUSE Opcode Register Description
Name: PAUSTMR
Bits
Name
15:0
Pause_Time
IPUG39_02.9, December 2010
Type
Default
R/W
0
R/W
1
Type
Default
Reserved
1 = loop back, 0 = no loop back
R/W
1
This bit is used to enable the loop back of packets on the client
side of the 10G+ MAC core.
R/W
0
Unused
Type
Default
Reserved
R/W
0
This bit controls the ignore_pkt pin on the 10G+ MAC core.
This bit gets ORed with the tx_fifo empty signal. The ORed output
R/W
0
controls the sine_tx_aem pin on the 10G+ MAC core.
R/W
0
Reserved
R/W
0
Reserved
1 = send request, 0 = don't send request
R/W
0
This bit gets ORed with the tx_fifo almost full signal. The ORed
output controls the tx_pausreq pin on the 10G+ MAC core.
Type
Default
These bits control the tx_paustim[15:0] pins on the 10G+ MAC
R/W
04FFH
core.
31
Address: A18H, A19H
Description
PAUSE Opcode. Upper byte
PAUSE Opcode. Lower byte
Address: B00H
Description
Address: B01H
Description
Address: B02H, B03H
Description
10 Gb+ Ethernet MAC IP Core User's Guide
Application Support
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