Signal Descriptions - Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual

Lattice Semiconductor

Signal Descriptions

Table shows the input and output ports of the MCDMA core that apply for both 8237 and non-8237 modes.
Table 4. Signal Definitions of the MCDMA Controller
Port Name
clk
cs_n
reset
ready
hlda
eopin_n
iorin_n
iowin_n
ain [AIN_BUS_WIDTH-1:0]
dbin [DATA_BUS_WIDTH-1:0]
dreq[N-1:0]
hreq
eopout_n
iorout_n
dbout [DATA_BUS_WIDTH-1:0]
iowout_n
memw_n
memr_n
Multi-Channel DMA Controller User's Guide
Type Active State
Input Rising Edge Clock. This signal controls and synchronizes the operations
of the MCDMA.
Input Low Chip Select. This is an active low signal used to select the
MCDMA.
Input High Reset. This is an active high signal that clears the internal
registers. After reset, the device is placed in the Idle state
and the DMA requests are masked.
Input High Ready. This is an active high signal used to extend the mem-
ory read and write pulses from the MCDMA. This is most of
often used to accommodate slow memories.
Input High Hold Acknowledge. This active high signal generated by the
CPU indicates the CPU has relinquished control of the sys-
tem buses.
Input Low End Of Process Input. This active low input permits the
external termination of the current DMA service.
Input Low I/O Read Input. This is an active low signal when asserted
along with cs_n. Thus, it permits the CPU to read the internal
registers of MCDMA.
Input Low I/O Write Input. This is an active low signal. When asserted
along with cs_n, it permits the CPU to write into the internal
registers of the MCDMA.
Input N/A Address. This signal selects one of the internal registers. In
the 8237 mode, ain is 4 bits wide. In the non-8237 mode, the
bus width depends on the number of channels selected.
Input N/A Data Bus Input. The CPU writes to the internal registers
through this data bus.
Input High/Low DMA Request. These programmable parity signals are asyn-
(8237) chronous signals generated by peripherals requesting DMA
High service. A device reset initializes dreq to active high.
(Non-8237) In 8237 mode, these parity signals are programmable to be
active high or low. In non-8237, these signals are always
active high.
Output High Hold Request. This is an active high signal sent to the CPU
to request control over the system bus.
Output Low End of Process Out. This active low signal indicates normal
termination of a DMA service.
Output Low I/O Read Output. This active low signal is used to access
data from a peripheral during a DMA Write transfer.
Output N/A Data Bus Output. This bus contains the value of the internal
register when read by the CPU. In the write-to-memory
phase of the memory-to-memory DMA operation, the dbout
data bus transmits the data from the temporary register.
Output Low I/O Write Output. This active low signal is used to load data
to a peripheral during a DMA Read transfer.
Output Low Memory Write. This active low signal is used to indicate that
data is being written to the selected memory location during a
DMA Write or a memory-to-memory transfer.
Output Low Memory Read. This active low signal is used to indicate that
data is being read from the selected memory location during
a DMA Read or a memory-to-memory transfer.
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Description