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The format of an untagged Ethernet frame is shown in
in
Figure
2-4.
Figure 2-3. Untagged Ethernet Frame Format
SOF
PREAMBLE
1 byte
6 bytes
Figure 2-4. Tagged Ethernet Frame Format
SOF
PREAMBLE
1 byte
6 bytes
The MAC is responsible for constructing a valid frame from the data received from the user's application before
transmitting it. On the receive path, it receives frames from the network through the XGMII interface and passes the
parameters of the frame to the MAC client (FIFO interface). The transmit path logic accepts the frame from the user
application through a FIFO interface. The fields of the Ethernet frame that are expected from the application inter-
face are shown in Figures 2-5 and 2-6.
On the transmit path, the MAC can be programmed in one of two modes. In the first mode
frame from the user contains the FCS along with the DESTINATION ADDRESS, SOURCE ADDRESS, LENGTH /
TYPE and Data the Transmit MAC adds the SOF, preamble and SFD before transmitting the frame. This mode can
be set by enabling the tx_pass_fcs bit in the TX_CTL register. In the second mode
the number of bytes to be padded as well (if required) in addition to the FCS for the entire frame and adds the SOF,
preamble and SFD before transmitting the frame.
Similarly, on the receive path, the MAC can be programmed to transfer the frame as it was received to the FIFO
(Promiscuous mode) or after stripping off the FCS and any pad fields. In all cases the SOF, preamble and SFD
bytes will always be stripped off the frame before it is transferred to the FIFO.
Figure 2-5. Ethernet Frame with Frame Check Sequence
DESTINATION
Figure 2-6. Ethernet Frame with out Frame Check Sequence
The core has a number of inputs, which are used to provide control of the various modes of operation. Registers
have been included at the top level of the FPGA. These registers are not part of the core. They are discussed in an
appendix. The functionality of the MAC core is described in the following sections.
Receive MAC
The receive MAC is responsible for receiving the incoming frames and transferring them to the FIFO. In the pro-
cess, it performs the following operations:
• Checks the frame for a valid SOF and SFD symbol.
• Determines whether the frame should be received by analyzing the Destination Address.
• Determines the type of the frame by analyzing the Length/Type field.
• Checks for any errors in the frame by recalculating the CRC and comparing it with the expected value.
IPUG39_02.9, December 2010
DESTINATION
SFD
ADDRESS
1 byte
6 bytes
DESTINATION
SFD
ADDRESS
1 byte
6 bytes
SOURCE
ADDRESS
ADDRESS
DESTINATION
SOURCE
ADDRESS
ADDRESS
Figure
2-3. The format of a tagged Ethernet frame is shown
SOURCE
LENGTH/
ADDRESS
6 bytes
2 bytes
SOURCE
TAG FIELD
ADDRESS
4 bytes
6 bytes
LENGTH/
DATA/PAD
TYPE
46-1500 bytes
LENGTH/
DATA/PAD
TYPE
46-1500 bytes
8
10 Gb+ Ethernet MAC IP Core User's Guide
Functional Description
DATA/
TYPE
PAD
46-1500 bytes
LENGTH/
DATA/
TYPE
PAD
2 bytes
46-1500 bytes
(Figure
2-5), when the
(Figure
2-6), the MAC calculates
FRAME CHECK
SEQUENCE
FRAME CHECK
SEQUENCE
4 bytes
FRAME CHECK
SEQUENCE
4 bytes
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