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Table 4-1. File List (Continued)
File
<username>.ipx
<username>_top.[v,vhd]
These are all of the files necessary to implement and verify the 10 Gb+ Ethernet MAC IP core in your own top-level
design. The following additional files providing IP core generation status information are also generated in the
"Project Path" directory:
• <username>_generate.log – Synthesis and map log file.
• <username>_gen.log – IPexpress IP generation log file.
The \<ten_gbe_eval> and subtending directories provide files supporting 10 Gb+ Ethernet MAC core evaluation.
The \<ten_gbe_eval> directory shown in
figurations of the 10 Gb+ Ethernet MAC. The \<username> subfolder (\ten_gbe_core0 in this example) con-
tains files/folders with content specific to the username configuration.
The \ten_gbe_eval directory is created by IPexpress the first time the core is generated and updated each time
the core is regenerated. A \<username> directory is created by IPexpress each time the core is generated and
regenerated each time the core with the same file name is regenerated. A separate \<username> directory is
generated for cores with different names, e.g. \<ten_gbe_core0>, \<ten_gbe_core1>, etc.
Instantiating the Core
The generated 10 Gb+ Ethernet MAC IP core package includes black-box (<username>_bb.v) and instance
(<username>_inst.v) templates that can be used to instantiate the core in a top-level design. Two example RTL top-
level reference source files are provided in
\<project_dir>\ten_gbe_eval\<username>\src\rtl\top\sc.
The top-level file ten_gbemac_top.v is the same top-level that is used in the simulation model described in the next
section. Designers may use this top-level reference as the starting template for the top-level for their complete
design. Included in ten_gbemac_top.v is logic, memory and clock modules supporting an XGMII interface loop
back capability, a register module supporting programmable control of the 10 Gb+ Ethernet MAC core parameters
and system processor interface via the LatticeSC integrated SYSBUS capability. Verilog source RTL for these mod-
ules is provided in \<project_dir>\ten_gbe_eval\<username>\src\rtl\template\sc. The top-level configuration is spec-
ified via the parameters defined in the ten_gbemac_defines.v file in
\<project_dir>\ten_gbe_eval\<username>\src\params. A description of the 10 Gb+ Ethernet MAC
parameters is in the parameters section of this document. A description of the 10 Gb+ Ethernet MAC register lay-
out for this reference design is provided in an appendix to this document.
The top-level file ten_gbemac_core_only_top.v supports the ability to implement just the 10 Gb+ Ethernet MAC
core itself. This design is intended only to provide an accurate indication of the device utilization associated with
the 10 Gb+ Ethernet MAC core and should not be used as an actual implementation example.
Running Functional Simulation
The functional simulation includes a configuration-specific behavioral model of the 10 Gb+ Ethernet MAC IP Core
(<username>_beh.v) that is instantiated in an FPGA top level along with a client-side interface loop back capability
module and register implementation module.
IPUG39_02.9, December 2010
The IPX file holds references to all of the elements of an IP or Module after it is generated from
the IPexpress tool (Diamond version only). The file is used to bring in the appropriate files during
the design implementation and analysis. It is also used to re-load parameter settings into the
IP/Module generation GUI when an IP/Module is being re-generated.
This file provides a module which instantiates the 10 Gb+ Ethernet MAC core. This file can be
easily modified for the user's instance of the 10 Gb+ Ethernet MAC core. This file is located in
the
<username>_eval/<username>_/src/rtl/top/ directory.
Figure 4-3
Description
contains files/folders with content that is constant for all con-
20
10 Gb+ Ethernet MAC IP Core User's Guide
IP Core Generation
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