Chapter 2. Functional Description - Lattice Semiconductor 10 Gb+ Ethernet MAC IP User Manual

This chapter provides a functional description of the 10 Gb+ Ethernet MAC IP core.
interface diagram for the 10 Gb+ Ethernet MAC IP.
Figure 2-1. 10 Gb+ Ethernet MAC Core Block Diagram
reset _ n reset _ n
tx_data[63:0] tx_data[63:0]
tx_data_avail tx_data_avail
tx_eof tx_eof
tx_empty tx_empty
tx_read tx_read
tx_is_paused tx_is_paused
tx_force_err tx_force_err
tx_byten[2:0] tx_byten[2:0]
tx_paustim[15:0] tx_paustim[15:0]
tx_pausereq tx_pausereq
vlan_tag_en
vlan_tag[15:0] vlan_tag[15:0]
rx_data[63:0] rx_data[63:0]
rx_write rx_write
rx_byten[2:0] _
rx_eof rx_eof
rx_error rx_error
rx_sof rx_sof
ignore_pkt ignore_pkt
IPUG39_02.9, December 2010
Functional Description
10Gb+ MAC
IP Core
10Gb+ MAC IP Core
6 10 Gb+ Ethernet MAC IP Core User's Guide
Chapter 2:
Figure 2-1 shows a top-level
txmac_clk txmac_clk
txd[63:0] txd[63:0]
txc[7:0] txc[7:0]
rxmac_clk rxmac_clk
rxd[63:0] rxd[63:0]
rxc[7:0] rxc[7:0]
tx_statvec[25:0]
tx_staten tx_staten
rx_statvec[27:0] rx_statvec[27:0]
rx_staten rx_staten
mac_addr[47:0] mac_addr[47:0]
mode[1:0] mode[1:0]
tx_cfg[3:0] tx_cfg[3:0]
rx_cfg[6:0] rx_cfg[6:0]
pause_opcode[15:0] pause_opcode[15:0]
tx_ipg[4:0] tx_ipg[4:0]
max_frm_len[13:0] max_frm_len[13:0]
mc_table[63:0] mc_table[63:0]
tx_rx_status[4:0]