Transmit Mac - Lattice Semiconductor 10 Gb+ Ethernet MAC IP User Manual

Lattice Semiconductor

Transmit MAC

The main functions of the Transmit MAC are:
• Data padding for short frames when FCS generation is enabled.
• Generation of a pause frame when the tx_pausreq signal is asserted.
• To stop frame transmission when a Pause frame is received by the Receive MAC.
• Implement link fault signaling logic and transmit appropriate sequences based on the remote link status.
The TX_CTL register controls the operation of this module. For every frame transmitted, a statistics vector is gener-
ated. The composition of the vector is shown in
Table 2-2. Transmit MAC Statistics Vector
Statistics Counters
This module provides counters for all of the bits in the statistics vectors. It also implements statistic counters from
RFC2819 and RMON. The width of the counters is specified through a parameter and can have a value from 16 to
40 bits for all devices. The counters are read through an interface that returns the complete counter value in
response to a read request. An acknowledgement is returned to indicate that the counter value on the read data
bus is valid. There are separate request, acknowledge, and data buses for transmit counters and receive counters.
The address bus is shared for transmit and receive counters. The Statistics Counter is a part of the reference
design. A list of statistic counters is provided in
PHY Interface
The Reconciliation sublayer interface is implemented as a 64-bit wide single edge data bus and an 8-bit wide single
edge control bus. To allow this interface to conform to the XGMII definition DDR I/O cells are added at the top level
of the FPGA when this core is implemented. To allow this interface to conform to the XAUI definition a
PCS/SERDES quad is added at the top level of the FPGA when this core is implemented. The top level file pro-
vided with this core contains the logic to implement one of these choices.
Register Description
There are no registers in this core. All control and status information is passed between this core and the top level
of the device through individual I/O ports on the core. Registers must be added to the top level to control and mon-
itor these ports. A reference description of a set of registers to do this is included as an appendix to this user's
guide.
IPUG39_02.9, December 2010
Table 2-2.
Bit Description
25 Long Frame Error
24 Terminate Error
23 Length Check Error
22 CRC Error
21 Underrun Error
20 Multicast Address
19 Broadcast Address
18 Tagged Frame
17 Jumbo Frame
16 MAC Control Inserted by Client
15 MAC Control Inserted by MAC
14 Transmit OK
13-0 Transmitted Bytes
Table 5-1 on page
10
Functional Description
25.
10 Gb+ Ethernet MAC IP Core User's Guide