Table of Contents
Advertisement
Lattice Semiconductor
Table 2-3. 10 Gb+ Ethernet MAC IP Core Input and Output Signals (Continued)
Port Name
Active State
rx_eof
rx_error
txmac_clk
txd[63:0]
High=control
txc[7:0]
Low=data
rxmac_clk
rxd[63:0]
High=control
rxc[7:0]
Low=data
mac_addr[47:0]
mode[1:0]
tx_cfg[3:0]
pause_opcode[15:0]
tx_ipg[4:0]
max_frm_len[13:0]
rx_cfg[6:0]
IPUG39_02.9, December 2010
I/O Type
High
Output
End of frame signal asserted with the last segment of the frame.
When asserted, indicates that the frame had a length error, a termination
High
Output
error, or a CRC error. This signal is qualified with the rx_eof signal.
156.25 MHz MAC transmit clock. Ethernet frame transmit data is output on
N/A
Input
the rising edge of this clock.
Single data rate Ethernet frame transmit data. Converted to double data
N/A
Output
rate XGMII transmit data signals with FPGA ODDR circuit elements exter-
nal to the IP core.
Asserted by the MAC to indicate on a per byte basis that the txd bus con-
Output
tains data or control. Converted to double data rate XGMII transmit control
signals with FPGA ODDR circuit elements external to the IP core.
156.25 MHz MAC receive clock. Receive data is presented to the receive
N/A
Input
MAC coincident with the rising edge of this clock.
Single data rate Ethernet frame receive data. Converted from double data
N/A
Input
rate XGMII receive data signals with FPGA IDDR circuit elements external
to the IP core.
Input
Indicates on a per byte basis that the rxd bus contains data or control.
Unicast address for the MAC. This address is received from or sent to the
N/A
Input
link from most significant byte to least significant byte. For MAC address:
AC-DE-48-00-00-80, AC is sent first and 80 is sent last.
Bit 0 (rx_en) - Enables the receive side of the MAC.
High
Input
Bit 1 (tx_en) - Enables the transmit side of the MAC.
Bit 0 (tx_pass_fcs) - When zero, the MAC generates and inserts FCS in
outgoing packets.
Bit 1 (transmit_pause_en) - Enables the transmit side of the MAC to sup-
port flow control.
High
Input
Bit 2 (tx_ipg_stretch) - Enables the transmit side of the MAC to insert the
proper amount of inter-frame gap to support matching rate of OC192.
Bit 3 (transmit_short) - Enables the transmit side of the MAC to transmit
short frames.
N/A
Input
Supplies opcode for transmit pause frames.
Specifies the amount of inter-frame gap in increments of 4 bytes.
N/A
Input
0 - indicates the minimum value of 8 bytes.
Specifies the maximum frame length. A frame longer than this will be
N/A
Input
marked as long.
Bit 0 (prms) - Enables the receive side of the MAC to receive frames without
doing any address filtering.
Bit 1 (rx_pass_fcs) - When zero, the MAC discards the FCS of incoming
packets after checking it.
Bit 2 (rx_pause_en) - Enables the receive side of the MAC to support flow
control.
Bit 3 (receive_all_mc) - Enables the receive side of the MAC to receive mul-
High
Input
ticast frames as per address filtering rules.
Bit 4 (receive_bc) - Enables the receive side of the MAC to receive broad-
cast frames.
Bit 5 (receive_short) - Enables the receive side of the MAC to receive short
frames.
Bit 6 (drop_mac_ctrl) - Enables the receive side of the MAC to drop MAC
Control packets before passing them on to client.
Description
12
10 Gb+ Ethernet MAC IP Core User's Guide
Functional Description
Advertisement
Table of Contents
Need help?
Do you have a question about the 10 Gb+ Ethernet MAC IP and is the answer not in the manual?